Standard-cell placement problem has drawn extensive research attention in VLSI/CAD ever since its appearance. Nowadays, in spite of wide use of hierarchical design methodology and floorplanning, the problem of placing standard-cells remains one of the important topics. This problem is becoming more challenging because of two reasons. First, the circuit sizes are growing dramatically. The Semiconductor Research Corporation (SRC) suggests that we should be able to place designs containing up to one million cells within 16 hours. Such a problem size means that there exists a huge space between the optimal solution and the best solution by any known heuristic. The second reason is the multi-objective placement process. In addition to the traditional objectives such as routability and timing, more issues must be taken into account during the placement, e.g., cross talk, power. The placement problem becomes harder when considering these objectives.
KeywordsSimulated Annealing Placement Problem Hierarchical Placement Terminal Propagation Semiconductor Research Corporation
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- 1.Generalization to non-zero length for such nets is straight forward.Google Scholar
- 2.It is very easy to extend our results to the case when aspect ratio is not equal to 1.Google Scholar
- 3.This is because the increment (by one) operation is faster than an add operation in most machines.Google Scholar
- 4.Unbalanced partitioning (used in min-cut placement) does not apply here, because bin annealing requires bins are roughly equal in size.Google Scholar
- 5.The comparison is made when the number of rows in the bin grids does not change after adjusting. Otherwise the wirelengths are not comparable.Google Scholar
- 6.For example, before the temperature change.Google Scholar
- 7.The author of  mentioned this issue in ISPD 2001.Google Scholar