Abstract
Following logic synthesis and circuit design, an integrated circuit is represented as a collection of interconnected rectangular modules of fixed dimensions. Timing constraints on signal propagation paths along sequences of connections are also specified. The task of circuit placement is to arrange the modules inside a prescribed rectangular region such that no two modules overlap, timing constraints are satisfied, and the estimated total wirelength needed to implement the connections is minimized. Thus, an algorithm for placement derives a suitable spatial characterization of a given circuit from a logical-temporal one.
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Chan, T.F., Cong, J., Kong, T.T., Shinnerl, J.R. (2003). Multilevel Circuit Placement. In: Cong, J., Shinnerl, J.R. (eds) Multilevel Optimization in VLSICAD. Combinatorial Optimization, vol 14. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3748-6_4
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DOI: https://doi.org/10.1007/978-1-4757-3748-6_4
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