High-Speed Flash ADCs
Designing high-speed flash ADCs in a deep submicron technology requires optimized architectures and building blocks. In this chapter, the design of a high-speed 6 bit converter is presented. In the first section, an introduction will be given to flash architectures, after which the design issues of the different building blocks of the converter will be discussed. At the end, the measured results of the implemented converter will be shown.
KeywordsReference Voltage NMOS Transistor PMOS Transistor Acquisition Speed Spurious Free Dynamic Range
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