High-Speed Flash ADCs

Design issues of a 6 bit, 1 GHz CMOS Flash ADC
  • Koen Uyttenhove
  • Michiel Steyaert
Chapter

Abstract

Designing high-speed flash ADCs in a deep submicron technology requires optimized architectures and building blocks. In this chapter, the design of a high-speed 6 bit converter is presented. In the first section, an introduction will be given to flash architectures, after which the design issues of the different building blocks of the converter will be discussed. At the end, the measured results of the implemented converter will be shown.

Keywords

Reference Voltage NMOS Transistor PMOS Transistor Acquisition Speed Spurious Free Dynamic Range 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Koen Uyttenhove
  • Michiel Steyaert

There are no affiliations available

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