Abstract
Designing high-speed flash ADCs in a deep submicron technology requires optimized architectures and building blocks. In this chapter, the design of a high-speed 8 bit converter is presented, following the discussion of analog pre-processing techniques necessary to reduce the power consumption and input capacitance of the converter. Three analog preprocessing techniques will be described, two of which will be used in the design of the 8-bit converter. The systematic design of an 8-bit interpolating/averaging converter will then be described and experimental results will be presented.
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Uyttenhove, K., Vandenbussche, J., Gielen, G., Steyaert, M. (2003). Folding/Interpolating ADCs. In: Rodríguez-Vázquez, A., Medeiro, F., Janssens, E. (eds) CMOS Telecom Data Converters. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3724-0_5
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DOI: https://doi.org/10.1007/978-1-4757-3724-0_5
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