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Current-Steering High-Speed D/A Converters for Communications

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CMOS Telecom Data Converters

Abstract

Modern broadband communication integrated circuits require as fundamental subcircuits digital to analog converters (DAC) exhibiting both high-speed and high-resolution [1]. Wide bit-count DACs working at sampling clock frequencies in the range of the hundred of MHz will continue to be required, hence dictating Nyquist-rate data conversion, as for instance to convert digital bitstreams into continuous-time signals prior to up-conversion mixers preceding RF transmitters in wireless systems or to drive digital cable communications modems. This high rates have also been hitherto required by high-resolution displays for computer graphics and modern HDTV systems, for which time-domain performance is of utmost relevance, although spectral performance demands are much more stringent for communication ICs in which DACs are used to synthesize complex waveforms for which frequency-domain high-performance has to be attained [2]. The development of future mobile communication systems (including both 3 G terminals and basestations) as well as the prospective use of ubiquitous communication systems will continue the trust towards high-performance DAC conversion stages.

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References

  1. H. Samueli, “Broadband Communications ICs: Enabling high-bandwidth connectivity in the home and office”, in Proc. IEEE 1999 ISSCC, Feb. 1999, pp. 26-30.

    Google Scholar 

  2. A.R. Bugeja, B.S. Song, P.L. Rakers and S.F. Gillig, “A 14-b, 100-MS/s CMOS DAC designed for spectral performance”, IEEE Journal of Solid-State Circuits, vol. 34, no. 12, December 1999, pp. 1719–1731.

    Article  Google Scholar 

  3. Randall L. Geiger, Philip E. Allen, Noel R. Strader, VLSI Design techniques for analog and digital circuits, McGraw-Hill International Editions, 1990.

    Google Scholar 

  4. Mikael Gustavsson, J. Jacob Wikner, and Nianxiong Nick Tan, CMOS Data Converters for Communications, Kluwer Academic Publishers, 2000.

    Google Scholar 

  5. K. Bult and G. J. M. Geelen, “An inherently linear and compact MOST-only current division technique,” IEEE J. Solid-State Circuits, vol. 27, Dec. 1992, pp. 1730–1735.

    Article  Google Scholar 

  6. R.S. Soin, F. Maloberti, and J. Franca, Analogue-Digital ASICs, Peter Peregrinus Ltd., 1991.

    Google Scholar 

  7. Paul Hendriks, “Specifying Communication DACs”, IEEE Spectrum, July 1997, pp. 58-69.

    Google Scholar 

  8. Naoki Kumazava, Noriyuki Fukushima, Naomi Ono, Hobuhiro Sakamoto, “An 8 bit 150 MHz converter with 2 Vp-p wide range output”, IEEE Symposium on VLSI Circuits, 1990, pp. 55-56.

    Google Scholar 

  9. Tsutomu Kamoto, Yukiro Akazawa, Mitsuru Shinagawa, “An 8-bit 2-ns Monolithic DAC”, IEEE Journal of Solid-State Circuits, vol. 23, no. 1, February 1998, pp. 142–146.

    Article  Google Scholar 

  10. Lauri Sumanen, Mikko Waltari, Kari Halonen, “A 10-bit High-Speed Low-Power CMOS D/A Converter in 0.2mm2”, IEEE Intl. Conference on Circuits and Systems, 1998, pp 15–18 vol. 1.

    Google Scholar 

  11. Nicholas van Bavel, “A 325 MHz 3.3V 10-Bit CMOS D/A Converter Core With Novel Latching Driver Circuit”, IEEE Custom Integrated Circuits Conference, 1998, pp. 245-247.

    Google Scholar 

  12. Jin-Park, Seung-Chul Lee, and Seung-Hoon Lee, “3V 10b 70MHz CMOS D/A converter for video applications”, Electronic Letters, vol. 35, no. 24, November 1999, pp. 2071–2073.

    Article  Google Scholar 

  13. Seung-Chul Lee, Jin Park, Jin-Sik Yoon, Jung-Hee Song, and Seung-Hoon Lee, “A 3 V 100 MS/s Digital-to-Analog Converter for Cable Modem Applications”, IEEE Transactions on Consumer Electronics, vol. 46, no. 4, November 2000, pp. 1043–1047.

    Article  Google Scholar 

  14. C-H. Lin, K. Bult, “A 10b 250Msample/s CMOS DAC in lmm2”, IEEE Intl. Solid-State Integrated Circuits Conference, 1998, pp. 214-215.

    Google Scholar 

  15. KI-Hong Ryu, Kwang Sub Yoon, Hing Ki Min, “Design of a 3.3V 12bit CMOS D/A Converter with a high linearity”, Proceedings. 1998 Midwest Symposium on Circuits and Systems, 1998, pp 538-541.

    Google Scholar 

  16. A. Marques, J. Bastos, A. Van den Bosch, J. Vandenbussche, M. Steyaert, W. Sansen, “A 12b Accuracy 300Msample/s Update Rate CMOS DAC”, IEEE Intl. Solid-State Integrated Circuits Conference, 1998, pp. 216-217.

    Google Scholar 

  17. A. Van den Bosch, M. Borremans, J. Vandenbussche, G. Van der Plas, A. Marques, J. Bastos, M. Steyaert, G. Gielen, W. Sansen, “A 12 bit 200 MHz Low Glitch CMOS D/A Converter”, IEEE Custom Integrated Circuits Conference, 1998, pp 249-252.

    Google Scholar 

  18. Bruce J. Tesch, and Juan C. Garcia, “A Low Glitch 14-b 100-MHz D/A Converter”, IEEE J. of Solid-State Circuits, vol. 32, no. 9, September 1997, pp. 1465–1469.

    Article  Google Scholar 

  19. Alex R. Bugeja, Bang-Sup Song, “A Self-Trimming 14b 100Msamples/s CMOS DAC”, IEEE Intl. Solid-State Integrated Circuits Conference, 2000, pp. 44-45.

    Google Scholar 

  20. Marcel J.M Pelgrom, Aad C. J. Duinmaijer, and Anton P.G. Welbers, “Matching Properties of MOS Transistors”, IEEE J. of Solid-State Circuits, vol. 24, no. 5, 1989, pp. 1433–1440.

    Article  Google Scholar 

  21. A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-Bandwidth Limitations for High Speed High Resolution Current Steering CMOS D/A Converters”, Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sept. 1999, pp 1193-1196.

    Google Scholar 

  22. J. Bastos, A.M. Marques, M.S.J. Steyaert, W. Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC”, IEEE J. of Solid-State Circuits, vol. 33, no. 12, 1998, pp. 1959–1969.

    Article  Google Scholar 

  23. Xavier Aragonès, José Luis Gonzalez, and Antonio Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Kluwer Academic Publishers. Boston, 1999.

    Google Scholar 

  24. Frank Herzel, and Behzad Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise”, IEEE Tr. on Circuits and Systems-II, vol. 46, no. 1, Jan. 1999, pp. 56–62.

    Article  Google Scholar 

  25. Patrik Larsson, “Resonance and Damping in CMOS Circuits with On-Chip Decoupling Capacitance”, IEEE Tr. on Circuits and Systems-I, Vol. 45, No. 8, Aug. 1998, pp. 849–858.

    Article  Google Scholar 

  26. M. Orshansky, L. Milor, Ly Nguyen, G. Hill, Yeng Peng, and Chenming Hu, “Intra-filed gate CD variability and its impact on circuit performance”, Intl. Electron Devices Meeting 1999 Technical Digest, 1999, pp. 479-482.

    Google Scholar 

  27. B.E. Stine, V. Mehrotra, D.S. Boning, J.E. Cung, and D.J. Ciplickas, “A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance”, Intl. Electron Devices Meeting 1997 Technical Digest., 1997, pp. 132-136.

    Google Scholar 

  28. J. M Fournier, P. Senn, “A 130-MHz 8-b CMOS Video DAC for HDTV Applications”, IEEE J. of Solid-State Circuits, vol. 26, no. 7, 1991. pp. 1073–1076.

    Article  Google Scholar 

  29. Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, N. Yazawa, “A 10-b 70-MS/s CMOS D/A converter”, IEEE J. of Solid-State Circuits, vol. 26, no. 4, 1991, pp. 637–642.

    Article  Google Scholar 

  30. G. Van der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, G. Gielen, “A 14-b Intrinsic Accuracy Q2-Random Walk CMOS DAC”, IEEE J. of Solid-State Circuits, vol. 34, no. 12, 1999, pp. 1708–1718.

    Article  Google Scholar 

  31. Yonghua Cong, and Randall L. Geiger, “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays”, IEEE Trans, on Circuits and Systems-II, vol. 47, no. 7, 2000, pp. 585–595.

    Article  Google Scholar 

  32. Chi-Hung Lin, and Klaas Bult, “A 10-b, 500-Msample/s CMOS DAC in 0.6 mm2”, IEEE J. of Solid-State Circuits, vol. 33, no. 12, 2000, pp. 1948–1958.

    Google Scholar 

  33. A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, “A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converter”, IEEE J. of Solid-State Circuits, vol. 36, no. 3, 2001, pp. 315–324.

    Article  Google Scholar 

  34. A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, “A 12b 500Msample/s Current-Steering CMOS D/A Converter”, Proc. of 2001 IEEE Intl. Solid-State Circuits Conference, 2001, pp. 366-367.

    Google Scholar 

  35. Alex R. Bugeja, and Bang-Sup Song, “A Self-Trimming 14.b 100-MS/s CMOS DAC”, IEEE J. of Solid-State Circuits, vol. 35, no. 12, 2000, pp. 1841–1852.

    Article  Google Scholar 

  36. Mika Tiilikainen, “A 1.8V 20mW lmm2 100MSample/s CMOS DAC”, Proc. of 26th European Solid-State Circuits Conference (ESSCIRC), 2000, pp.

    Google Scholar 

  37. J.L Gonzalez, Eduard Alarcón, “Clock-Jitter Induced Distortion in High-Speed CMOS Switched-Current Segmented Digital-to-Analog Converters”, Proceedings of the IEEE Intl. Symposium on Circuits and Systems (ISCAS’01), Sydney, Australia, May 2001, pp. I-512-I-515.

    Google Scholar 

  38. Selim Saad Award, “Analysis of Accumulated Timing-Jitter in the Time Domain”, IEEE Tr. on Instrumentation and Measurement, vol. 47, no. 1, Feb. 1988, pp. 69–73.

    Google Scholar 

  39. Harau Kobayashi, Masanao Morimura, Kensuke Keboyashi, and Yoshitaka Onaya, “Aperture Jitter Effects in Wideband Sampling Systems”, Proc. of IMTC’99 Conference, 1999, pp. 880-885.

    Google Scholar 

  40. J.L González, Eduard Alarcón, “Study of Delta-I Noise Effects on the Spectral Performance of Current-Steering Segmented Digital-to-Analog Converters”, Proceedings of the 5th IEEE Workshop on Signal Propagation on Interconnects (SPI’01), Cavallino-Venice, Italy, May 2001.

    Google Scholar 

  41. A. Van den Bosch, M. Steyaert, W. Sansen, “Design Techniques for High Accuracy, Current-Steering CMOS D/A Converters”, 3rd Workshop on ADC Modelling and Testing, 1998, pp. 861-866.

    Google Scholar 

  42. Hiroyuki Kohno, Yasuyuki Nakamura, Atsuhito Kondo, Hiroyuki Amishiro, Takahiro Miki, Keisuke Okada, “A 350-MHz 8-bit CMOS D/A Converter Using Delayed Driving Scheme”, Proc. of IEEE 1995 Custom Integrated Circuits Conference, pp. 211-214, 1995.

    Google Scholar 

  43. D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley & Sons, 1997.

    Google Scholar 

  44. Seung-Chul Lee, Jin Park, Jin-Sik Yoon, Jung-Hee Song, and Seung-Hoon Lee, “A 3 V 10b 100 MS/s Digital-to-Analog Converter for Cable Modem Applications”, Proc. of IEEE 1998 ICECS, 1998, pp. 203-205.

    Google Scholar 

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Authors
  1. José Luis González
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  2. Eduard Alarcón
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Editor information

Editors and Affiliations

  1. Institute of Microelectronics of Seville, Spanish Microelectronics Center, IMSE-CNM (CSIC) and Department of Electronics, University of Seville, Spain

    Angel Rodríguez-Vázquez  & Fernando Medeiro  & 

  2. ST Microelectronics, Belgium

    Edmond Janssens

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Luis González, J., Alarcón, E. (2003). Current-Steering High-Speed D/A Converters for Communications. In: Rodríguez-Vázquez, A., Medeiro, F., Janssens, E. (eds) CMOS Telecom Data Converters. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3724-0_3

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  • DOI: https://doi.org/10.1007/978-1-4757-3724-0_3

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5382-7

  • Online ISBN: 978-1-4757-3724-0

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