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CMOS Telecom Data Converters pp 523–559Cite as

Design Methodologies for Sigma-Delta Converters

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Abstract

Oversampling converters have become very popular due to their ability to solve problems found in other architectures, like the need for high-accuracy analog antialiasing filtering and the large sensitivity to circuit imperfections and noisy environments.

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References

  1. F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators. Kluwer, 1999.

    Google Scholar 

  2. G.E. Gielen and J.E. Franca, “CAD Tools for Data Converter Design: An Overview”, IEEE Trans. on Circuits and Systems II, vol. 43, no. 2, pp. 77–89, Feb. 1996.

    Article  Google Scholar 

  3. V. F. Dias, V. Liberali and F. Maloberti, “Design Tools for Oversampling Data Converters: Needs and Solutions”. Microelectronics Journal, vol. 23, pp. 641–650, 1992.

    Article  Google Scholar 

  4. C. H. Wolff and L. Carley: “Simulation of Δ-Σ Modulators Using Behavioral Models”, Proc. IEEE Int. Symp. on Circuits and Systems, pp. 376-379, 1990.

    Google Scholar 

  5. V. Liberali, V.F. Dias, M. Ciapponi and F. Maloberti, “TOSCA: a Simulator for Switched-Capacitor Noise-Shaping A/D Converters,”, IEEE Trans. Computer-Aided Design, vol. 12, no. 9, pp. 1376–1386, Sept. 1993.

    Article  Google Scholar 

  6. F. Medeiro, B. Pérez-Verdú, A. Rodríguez-Vázquez and J.L. Huertas, “A Vertically Integrated Tool for Automated Design of SD Modulators,”, IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 762–772, July 1995.

    Article  Google Scholar 

  7. K. Francken, P. Vancorenland and G. Gielen, “DAISY: a simulation-based high-level synthesis tool for ΔΣ modulators,” Proc. IEEE/ACM Int. Conf. Computer-Aided Design, pp. 188-192,2000.

    Google Scholar 

  8. G.T. Brauns, R.J. Bishop, M.B. Steer, J.J. Paulos and S.H. Ardalan, “Table-based Modeling of delta-sigma modulators using ZSIM,” IEEE Trans. Computer-Aided Design, pp. 142–150, Vol. 9, No. 2, Feb. 1990.

    Article  Google Scholar 

  9. R. del Río, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez, “Reliable analysis of settling errors in SC integrators-application to the design of high-speed ΣΔ modulators,” Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, pp. 417–420, 2000.

    Google Scholar 

  10. R. del Rio, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez, “Reliable analysis of settling errors in SC integrators: application to ΣΔ modulators,”, IEE Electronic Letters, vol. 36, no. 6, pp. 503–504, Mar. 2000.

    Article  Google Scholar 

  11. K. Lee and R. G. Meyer, “Low Distortion Switched-Capacitor Filter Design Techniques”, IEEE Journal of Solid-State Circuits, vol. 20, pp. 1103–1113, Dec. 1985.

    Article  Google Scholar 

  12. C.B. Wang, “A 20-bit 25-kHz Delta-Sigma A/D Converter Utilizing a Frequency-Shaped Chopper Stabilization Scheme,”, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 566–569, March 2001.

    Article  Google Scholar 

  13. W. Bennett: “Spectra of Quantized Signals”, Bell Syst. Tech. J, Vol. 27, pp. 446–472, July 1948.

    Google Scholar 

  14. IEEE VHDL Language Reference Manual, IEEE Std 1076-2002.

    Google Scholar 

  15. IEEE VHDL 1076.1 Language Reference Manual, IEEE Std 1076.1-1999.

    Google Scholar 

  16. M. Degrauwe et al., “IDAC: An Interactive Design Tool for Analog CMOS Circuits,” IEEE J. Solid-State Circuits, vol. 22, pp. 1106–1114, Dec. 1987.

    Article  Google Scholar 

  17. G. Beenker, J.D. Conway, G. Schrooten and A. Slenter, “Analog CAD for Consumer IC’s,” Proc. Workshop on Advances in Analog Circuit Design, pp. 343-355, 1992.

    Google Scholar 

  18. M.F. Mar and R.W. Brodersen, “A Design System for On-Chip Oversampling A/D Interfaces,” IEEE Trans, on VLSI Systems, vol. 3, pp. 345–354, Sept. 1995.

    Article  Google Scholar 

  19. P. J. M. Laarhoven and E.H.L. Aarts: “Simulated Annealing: Theory and Applica-tions”, Kluwer, 1987.

    Google Scholar 

  20. R. Harjani, R. Rutenbar and L.R. Carley: “OASYS: A Framework for Analog Circuits Synthesis”, IEEE Trans. Computer-Aided Design, Vol. 8, pp. 1247–1265, December 1989.

    Article  Google Scholar 

  21. H. Y. Koh, C.H. Sequin and P.R. Gray: “OPASYN: A Compiler for CMOS Operational Amplifier”, IEEE Trans. Computer-Aided Design, Vol. 9, pp. 113–125, February 1990.

    Article  Google Scholar 

  22. G. Gielen, H. Walscharts and W. Sansen, “Analog Circuits Design Optimization Based on Symbolic Simulation and Simulated Annealing”, IEEE J. Solid-State Circuits, vol. 25, pp. 707–713, June 1990.

    Article  Google Scholar 

  23. W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli and A.L. Tits, “DELIGHT.SPICE: An Optimization-Based System for the Design of Integrated Circuits”, IEEE Trans. Computer-Aided Design, vol. 7, pp. 501–519, April 1988.

    Article  Google Scholar 

  24. F. Medeiro, R. Rodríguez-Macías, F.V. Fernández, R. Domínguez-Castro, J.L. Huertas and A. Rodríguez-Vázquez, “Global Design of Analog Cells Using Statistical Optimization Techniques”, Analog Integrated Circuits and Signal Processing, vol. 6, no. 3, pp. 179–195, Kluwer, Nov. 1994.

    Article  Google Scholar 

  25. R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley and J.R. Heliums, “Anaconda: Simulation-Based Synthesis of Analog Circuits Via Stochastic Pattern Search,”, IEEE Trans. Computer-Aided Design, vol. 19, no. 6, pp. 703–717, June 2000.

    Article  Google Scholar 

  26. J. Rijmenants, et al., “ILAC: An Automated Layout Tool for Analog CMOS Circuits,” IEEE J. Solid-State Circuits, vol. 24, pp. 417–425, April 1989.

    Article  Google Scholar 

  27. J.M. Cohn, R.A. Rutenbar and L.R. Carley, “KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing.”, IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 330–342, March 1991.

    Article  Google Scholar 

  28. K. Lampaert, G. Gielen and W. Sansen, “A Performance-Driven Placement Tool for Analog Integrated Circuits.”, IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 773–780, July 1995.

    Article  Google Scholar 

  29. J.D. Conway and G.G. Schrooten, “An Automatic Layout Generator for Analog Circuits,” Proc. IEEE European Design Automation Conf., pp. 513-519, 1992.

    Google Scholar 

  30. R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez, “Generation of Technology-Independent Retargetable Analog Blocks,”, Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp. 157–170, Kluwer, Nov. 2002.

    Article  Google Scholar 

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Authors
  1. Francisco V. Fernández
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  2. Rocío del Río
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  3. Rafael Castro-López
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  4. Oscar Guerra
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  5. Fernando Medeiro
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  6. Belén Pérez-Verdú
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Editor information

Editors and Affiliations

  1. Institute of Microelectronics of Seville, Spanish Microelectronics Center, IMSE-CNM (CSIC) and Department of Electronics, University of Seville, Spain

    Angel Rodríguez-Vázquez  & Fernando Medeiro  & 

  2. ST Microelectronics, Belgium

    Edmond Janssens

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Fernández, F.V., del Río, R., Castro-López, R., Guerra, O., Medeiro, F., Pérez-Verdú, B. (2003). Design Methodologies for Sigma-Delta Converters. In: Rodríguez-Vázquez, A., Medeiro, F., Janssens, E. (eds) CMOS Telecom Data Converters. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3724-0_15

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  • DOI: https://doi.org/10.1007/978-1-4757-3724-0_15

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5382-7

  • Online ISBN: 978-1-4757-3724-0

  • eBook Packages: Springer Book Archive

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