Routing Clock On Package

Abstract

Traditionally, the global clock distribution tree or network is routed on the top metals of the chip. The metal thickness and width in the highest metal layer are larger than those in the lower layers. Furthermore, the wires comprising the package layer are even wider and thicker, with usually a 1–2 order larger line scale than the on-chip interconnects. The interconnect resistance on package is 2–4 order less than the on-chip metal resistance. Based on flip chip technology and area I/Os, the global clock tree or network can be routed on the package. The layout design of the chip becomes easier by separating the global clock network from the rest. The clock trees on the package layers still have few obstacles to overcome before it is applied to the real chips, which will be studied in this chapter. Section 9.1 presents an overview. Section 9.2 discusses the ESD design. Section 9.3 shows the noise considerations. Section 9.4 shows the experimental results on a microprocessor test chip. Section 9.5 provides a summary to this chapter.