Because of the importance of the clock circuit, designers have been verifying in detail the clock networks for microprocessor chips and ASIC chips [99,107]. The manual approach of simulating each stage of the clock buffer tree has been widely used in the design of most chips, although the automation CAD tools for the entire clock network analysis are available nowadays [107,112]. The manual approach usually consists of the following procedures for the clock tree analysis: (a) identify the entire clock tree; (b) separate the clock network into the stages; (c) extract RC data of the clock lines at each stage; (d) simulate each stage of the clock tree including the RC line models and buffer models; and (e) piece the simulation results together to trace the clock delays from the root to the end points. The delay for each stage is measured at the inputs of the buffers to the inputs of the next stage. The above approach may not be feasible for the clock mesh structure such as in the Alpha microprocessor chip . Section 7.1 introduces the RC extraction flow for clock network. Section 7.2 demonstrates the clock tree tracing and RC stitching capability by a CAD tool . Section 7.3 shows the simulation methods and report files for clock networks. Section 7.4 discusses the effects of the IR drop in the power supply network on the clock skew analysis. Section 7.5 gives the summary to this chapter.
KeywordsPower Grid Local Clock Clock Tree Clock Distribution Clock Network
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