Microprocessor Clock Distribution Examples

Abstract

Aggressive clock skew control is always one of major efforts in the microprocessor design. Any clock skew reduction adds directly to the available cycle time. Many techniques have been explored in the clock design for high-performance microprocessors. Traditionally, the clock networks are routed in two hierarchies: the global clock network and the local clock networks. Balanced clock trees or clock grids are usually used to minimize the clock skew in the clock distribution. In recent years, the de-skewing buffers are added in the local clock network to further reduce the clock skew for the full-chip clock distribution. Section 6.1 shows the clock distribution scheme in an Intel IA-64 microprocessor design [83]. Section 6.2 presents the Intel Pentium IV clock distribution scheme [64]. Section 6.3 describes the Intel Pentium III clock distribution method [85,86]. Section 6.4 discusses the DEC Alpha chip clock distribution methodology [98]. Section 6.5 shows the IBM PowerPC clock distribution design considerations [101,102]. Section 6.6 contains a summary of this chapter.