Overview to Timing Constraints

  • Qing K. Zhu


The sequential elements or storage elements in the digital circuits restore the data. The sequential elements include the flip-flop and latch circuits, which change the saved data based on the rising or falling clock pulses. The timing constraints of sequential elements (flip-flops and latches) define the minimum time intervals between data signals and clocks. They specify when signals must be ready in order to ensure the correct functioning of the sequential circuits Timing constraints includes the following items: the setup time, the hold time, the recovery time, and the minimum pulse width. An example of a hold time problem arises from excessively long clock delay compared to the data delay.


Setup Time Hold Time Data Path Clock Signal Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 2003

Authors and Affiliations

  • Qing K. Zhu
    • 1
  1. 1.Intel CorporationT-RAM Inc.USA

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