Abstract
The sequential elements or storage elements in the digital circuits restore the data. The sequential elements include the flip-flop and latch circuits, which change the saved data based on the rising or falling clock pulses. The timing constraints of sequential elements (flip-flops and latches) define the minimum time intervals between data signals and clocks. They specify when signals must be ready in order to ensure the correct functioning of the sequential circuits Timing constraints includes the following items: the setup time, the hold time, the recovery time, and the minimum pulse width. An example of a hold time problem arises from excessively long clock delay compared to the data delay.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Zhu, Q.K. (2003). Overview to Timing Constraints. In: High-Speed Clock Network Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3705-9_2
Download citation
DOI: https://doi.org/10.1007/978-1-4757-3705-9_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5336-0
Online ISBN: 978-1-4757-3705-9
eBook Packages: Springer Book Archive