Balanced Clock Routing Algorithms

Abstract

The balanced clock routing algorithms have been researched by many people [7–16]. The goal is to develop a CAD tool, which can route the clock trees in the balanced form to minimize the clock skew. We will summarize the CAD algorithms developed by the author in the Ph.D. dissertation [122, 15,29]. Section 10.1 shows an algorithm to construct a planar equal path length clock tree. Section 10.2 discusses the embedding approach to transform an equal path clock tree with Manhattan wires. Section 10.3 shows a skew-bounded clock tree refinement method. Section 10.5 describes wire sizing technique and optimization flow for the clock skew reduction. Section 10.6 provides a summary of this chapter.