Clock distribution is one of the limiting factors for the high frequency chip design. Device technology improvement, such as deepsubmicron with faster transistors, can only marginally solve the clock distribution problem because the interconnect delay becomes the significant factor in the clock cycle time. Section 1.1 provides the introduction to clock frequency and power issues. Section 1.2 explains the sources of the clock skew and clock jitter, which are two major design issues in the clock network design. Section 1.3 shows the PVT effects on the clock skew. Section 1.4 describes the clock buffer design. Section 1.5 discusses the power supply and reliability for clock distribution. Section 1.6 demonstrates the design complexity of the clock distribution network by using a microprocessor example. Section 1.7 provides the summary to this chapter.
KeywordsBuffer Size Clock Frequency Local Clock Reference Clock Clock Tree
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