Formal Cache Analysis in SYMTA

  • Fabian Wolf


Caches in the target architecture often increase the performance of the system because they can bridge the gap between processor speed and memory access time. They potentially reduce system power consumption because external memory does not need to be activated on cache hits. It is hard to guarantee that real-time constraints are met when caches are used because cache behavior prediction is difficult in general. Caches can even decrease the performance of the processor when a complete cache line is loaded on a miss which results in a higher latency than a single access to main memory. The accurate prediction of cache behavior has not yet been sufficiently solved because its dependencies on control and data flow are very complex.


Basic Block Data Cache Cache Line Embed Software Control Flow Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 2002

Authors and Affiliations

  • Fabian Wolf
    • 1
  1. 1.Technische Universität BraunschweigGermany

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