Abstract
Today’s electronic technology is based on the design and manufacture of integrated circuits. The concept of the integrated circuit comes from the work of 2000 Nobel Prize winner J.S. Kilby [1]. Its origins can be dated to February 1959. In his patent declaration, Kilby defines the integrated circuit with the following statement: “this invention relates to miniature electronic circuits, and more particularly to unique integrated electronic circuits fabricated from semiconductor material”.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Kilby, J.S., “The integrated circuit’s early history”, Proceedings IEEE, vol. 88, no. 1, January 2000, pp. 109–111.
Tsividis, Yannis P, “Operation and modelling of the MOS transistor”, McGraw Hill, 1989.
Uyemura, J.P., “Fundamentals of MOS digital integrated circuits”, Addisson-Wesley, 1988.
Pidin, S. et al., “Experimental and simulation study on sub-50nm CMOS design”, Proceedings Symposium on VLSI Technology 2001, pp. 35–36.
Bondypadhyay, P.K., “Moore’s law governs the silicon revolution”, Proceedings IEEE, vol. 86, no. 1, January 1998, pp. 78–81.
Hamilton, S., “Taking Moore’s law into the next century”, Computer, vol. 32, no. 1, January 1999, pp. 43–48.
Sze, S.M., “Physics of Semiconductor Devices”, New York, Wiley, 1981.
Asano, K. et al., “Patterning sub-30nm MOSFET gate with i-line lithography”, IEEE Transactions on Electron Devices, vol. 48, no. 5, May 2001, pp. 1004–1006.
Segura, J.A. and Rubio, A., “A detailed analysis of CMOS SRAMS with gate oxide shorts defects”, IEEE Journal Solid State Circuits, vol. 32, no. 10, October 1997, pp. 1543–1550.
Renovell, M. et al., “Boolean and current detection of MOS transistor with gate oxide shorts”, Proceedings International Test Conference 2001, pp. 1039–1048.
Semenov, O. and Sachdev, M., “Impact of technology scaling on bridging fault detection in sequential and combinational CMOS circuits”, Proceedings International Workshop on Defect Based Testing 2000, pp. 36–42.
Rodriguez-Montanés,R., Bruis, E.M.J.G. and Figueras, J., “Bridging defects resistance measurements in a CMOS process”, Proceedings International Test Conference 1992, p. 892.
Champac, V.H., Figueras, J. and Rubio, A., “Electrical model of the floating gate defect in CMOS IC’s: implications on Iddq testing”, IEEE Transactions on Computer-AidedDesign of Circuits and Systems, vol. 13, no. 3, March 1994, pp. 359–369.
Segura, J. et al., “Quiescent current analysis and experimentation of defective CMOS circuits”, Journal of Electronic Testing: Theory and Application,3, 337–348(1992), Kluwer Academic Publishers.
Segura, J. et al., “A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors”, Journal of Electronic Testing: Theory and Application,8, 229–239(1996), Kluwer Academic Publishers.
Avizienis, A. and Laprie, J.C., “Dependable computing: from concepts to design diversity”, Proceedings of the IEEE, vol. 74, no. 8, May 1986.
Abramovici, M., Breuer, M.A. and Friedman, A.D., Digital Systems Testing and Reliable Design, Computer Science Press, 1990.
Abraham, J A and Fuchs, W.K., “Fault and error models for VLSI”, Proceedings of the IEEE, vol. 74, no. 5, May 1986.
Breuer, M.A. and Friedman, A.D., “Diagnosis and reliable design of digital systems”, Computer Science-Press, Washington DC 1976.
Wadsack, R.L., “Fault modelling and logic simulation of CMOS and MOS integrated circuits”, Bell System Technology Journal, pp. 1449–1474, May-June 1978.
Abraham, J.A. and Parker, K.P., “Practical Microprocessor Testing: Open and closed loops approaches”, Proc. COMPCON Spring 1981, pp. 308–311, February 1981.
Sharma, M. and Patel, J.H., “Testing of critical paths for delay faults”, Proceedings of the International Test Conference 2001, pp. 634–641.
Tyszer, J., “Testing of three-stage switching networks for coupling faults”, IEEE Transactions on Communications, vol. 40. no. 2, Feb. 1992, pp. 413–422.
Kuo-Liang Cheng; Ming-Fu Tsai; Cheng-Wen Wu, “Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories”, IEEE Proceedings VLSI Test Symposium 2001, pp. 225–230.
Rubio, A.; Itazaki, N.; Xu, X.; Kinoshita, K., “An approach to the analysis and detection of crosstalk faults in digital VLSI circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 3, March 1994, pp. 387–395.
Milne, A.; Taylor, D.; Saunders, J.; Talbot, A.D., “Generation of optimised fault lists for simulation of analogue circuits and test programs”, IEE Proceedings Circuits, Devices and Systems, vol. 146, no. 6, Dec. 1999, pp. 355–360.
Gulati, R.K. and Hawkins, C.F. editors, “IDDQ testing of VLSI circuits”, Kluwer Academic Publishers, 1993.
McCluskey, E.J., “Logic Design Principles: with emphasis on testable semicustom circuits”, Prentice Hall International, 1986.
Fujiwara, H., “Logic testing and design for testability”, The MIT Press, 1985.
Chujen Lin; Haynes, L.; Mandava, P.; Prasad, P., “Automatic BIST design tool for mixed-signal circuits”, AUTOTESTCON ‘88 IEEE Systems Readiness Technology Conference, 1998 IEEE, pp. 97–102.
Roth, J.P., “Computer logic, testing and verification”, Computer Science Press, Rockville, Maryland, 1980.
Fujiwara, H. and Shimono, T., “On the acceleration of test pattern generation algorithms”, IEEE Transactions on Computers, vol. C-32, no. 12, pp. 1137–1144, December 1983.
Schulz, M.H. et al., “Improved deterministic test pattern generation with applications to redundancy identification”, IEEE Transactions on Computer-Aided-Design, vol. 8, no. 7, pp. 811–816, July 1989.
Franklin, M.; Saluja, K.K.; Kinoshita, K., “Design of a BIST RAM with row/column pattern sensitive fault detection capability”, Proceedings International Test Conference, 1989, pp. 327–336.
Mohammad, M.Gh.; Saluja, K.K.; Yap, A., “Testing flash memories”, Thirteenth International Conference on VLSI Design, 2000, pp. 406–411.
Das, D.K.; Bhattacharya, B.B.; Ohtake, S.; Fujiwara, H., “Testable design of sequential circuits with improved fault efficiency”, Fourteenth International Conference on VLSI Design, 2001, pp. 128–133.
Heragu, K.; Patel, J.H.; Agrawal, V.D., “A test generator for segment delay faults”, Proceedings, Twelfth International Conference On VLSI Design, 1999, pp. 484–491.
Wangning Long; Zhongchen Li; Shiyuan Yang; Yinghua Min, “Memory efficient ATPG for path delay faults”, Proceedings Test Symposium, 1997, pp. 326–331.
Kondo, H.; Kwang-Ting Cheng, “An efficient compact test generator for I/sub DDQ/ testing”, Proceedings of the Fifth Asian Test Symposium, 1996, pp. 177–182.
Isern, E.; Figueras, J., “Test generation with high coverage for quiescent current test of bridging faults in combinational circuits”, Proceedings International Test Conference, 1993, pp. 73–82.
IEEE standard test access port and boundary-scan architecture, IEEE Std 1149.1–2001.
IEEE standard for a mixed-signal test bus, IEEE Std 1149. 4–1999, 28 March 2000.
Konemann, P., Mucha, J. and Zwiehoff, G., “Built-in logic block observation technique”, Proceedings of the IEEE Test Conference, 1979.
Varma, P., Ambler, A.P. and Baker, K., “An analysis of the economics of self test”, Proceedings of the IEEE Test Conference, 1984.
Bernard, S.; Azais, F.; Bertrand, Y.; Renovell, M., “Analog BIST generator for ADC testing”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 338–346.
Seongwon Kim; Soma, M., “An all-digital built-in self-test for high-speed phase-locked loops”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 2, Feb. 2001, pp. 141–150.
Peralias, E.J.; Huertas, G.; Rueda, A.; Huertas, J.L, “Self-testable pipelined ADC with low hardware overhead”, IEEE Proceedings on VLSI Test Symposium, 2001, pp. 272–277.
Turino, J., “Test economics in the 21st century”, IEEE Design and Test of Computers, July-September 1997, pp. 41–44.
Ungar, L.Y. and Ambler, T., “Economics of built-in self-test”, IEEE Design and Test of Computers, September-October 2001, pp. 70–79.
Zorian, Y., Dey, S. and Rodgers, M.J., “Test of future System-On-Chips”, Proceedings of the International Conference on Computer Aided Design, 2000, pp. 392–398.
Lee, T.H. and Wong, S.S., “CMOS RF Integrated Circuits at 5 GHz and Beyond”, Proceedings of the IEEE, vol. 88, no. 10, October 2000, pp. 1560–1571.
Pynn, C.T., “Analyzing Manufacturing Test Costs”, IEEE Design and Test of Computers, July-September 1997, pp. 36–41.
Rajsuman, R., “Iddq testing for CMOS VLSI”, Proceedings of the IEEE, vol. 88, no. 4, April 2000, pp. 544–566.
Kundu, S., “Iddq defect detection in deep sub-micron CMOS ICs”, Proceedings of the Asian Test Symposium, 1998, pp. 150–152.
Zarrinfar, F. and Rajsuman, R., “Automated Iddq testing from CAD to manufacturing”, Proceedings International Workshop on Iddq testing“, 1995, pp. 48–51.
Hawkins, C.F. et al., “Quiescent power supply current measurements for CMOS IC defect detection”, IEEE Transactions on Industrial Electronics, May 1989, pp. 211–218.
Cusey, J.P. and Patel, J.H., “BART: A bridging fault test generator for sequential circuits”, Int. Test Conference, 1997, pp. 823–832.
Mao, W. et al., Quietest: A quiescent current testing methodology for detecting leakage faults“, Int. Conf. Computer Aided Design, 1990, pp. 280–283.
Rullan, M. et al., “Analysis of Issq/Iddq testing implementation and circuit partitioning in CMOS cell based design”, European Design and Test Conference, 1996, pp. 584–588.
Sah, C.T., “Characteristics of the Metal-Oxide-Semiconductors Transistors”, IEEE Trans. Electron Devices, ED-11, 324, 1964.
Proc. Int. Technology Roadmap for semiconductor, November 1999.
Szekely, V.; Rencz, M.; Torok, S.; Courtois, B., “Cooling as a possible way to extend the usability of I/sub DDQ/ testing”, Electronics Letters, Volume: 33 Issue: 25, 4 Dec. 1997, pp. 2117–2118.
Singer, G., “The future of test and DFT”, IEEE Design and Test, July-September 1997, pp. 11–16.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Altet, J., Rubio, A. (2002). Introduction to the testing of integrated circuits. In: Thermal Testing of Integrated Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3635-9_1
Download citation
DOI: https://doi.org/10.1007/978-1-4757-3635-9_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5287-5
Online ISBN: 978-1-4757-3635-9
eBook Packages: Springer Book Archive