Introduction to the testing of integrated circuits

  • Josep Altet
  • Antonio Rubio


Today’s electronic technology is based on the design and manufacture of integrated circuits. The concept of the integrated circuit comes from the work of 2000 Nobel Prize winner J.S. Kilby [1]. Its origins can be dated to February 1959. In his patent declaration, Kilby defines the integrated circuit with the following statement: “this invention relates to miniature electronic circuits, and more particularly to unique integrated electronic circuits fabricated from semiconductor material”.


Metal Oxide Semiconductor Test Vector Realistic Defect Delay Fault Automatic Test Equipment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    Kilby, J.S., “The integrated circuit’s early history”, Proceedings IEEE, vol. 88, no. 1, January 2000, pp. 109–111.CrossRefGoogle Scholar
  2. [2]
    Tsividis, Yannis P, “Operation and modelling of the MOS transistor”, McGraw Hill, 1989.Google Scholar
  3. [3]
    Uyemura, J.P., “Fundamentals of MOS digital integrated circuits”, Addisson-Wesley, 1988.Google Scholar
  4. [4]
    Pidin, S. et al., “Experimental and simulation study on sub-50nm CMOS design”, Proceedings Symposium on VLSI Technology 2001, pp. 35–36.Google Scholar
  5. [5]
    Bondypadhyay, P.K., “Moore’s law governs the silicon revolution”, Proceedings IEEE, vol. 86, no. 1, January 1998, pp. 78–81.CrossRefGoogle Scholar
  6. [6]
    Hamilton, S., “Taking Moore’s law into the next century”, Computer, vol. 32, no. 1, January 1999, pp. 43–48.CrossRefGoogle Scholar
  7. [7]
    Sze, S.M., “Physics of Semiconductor Devices”, New York, Wiley, 1981.Google Scholar
  8. [8]
    Asano, K. et al., “Patterning sub-30nm MOSFET gate with i-line lithography”, IEEE Transactions on Electron Devices, vol. 48, no. 5, May 2001, pp. 1004–1006.CrossRefGoogle Scholar
  9. [9]
    Segura, J.A. and Rubio, A., “A detailed analysis of CMOS SRAMS with gate oxide shorts defects”, IEEE Journal Solid State Circuits, vol. 32, no. 10, October 1997, pp. 1543–1550.CrossRefGoogle Scholar
  10. [10]
    Renovell, M. et al., “Boolean and current detection of MOS transistor with gate oxide shorts”, Proceedings International Test Conference 2001, pp. 1039–1048.Google Scholar
  11. [11]
    Semenov, O. and Sachdev, M., “Impact of technology scaling on bridging fault detection in sequential and combinational CMOS circuits”, Proceedings International Workshop on Defect Based Testing 2000, pp. 36–42.Google Scholar
  12. [12]
    Rodriguez-Montanés,R., Bruis, E.M.J.G. and Figueras, J., “Bridging defects resistance measurements in a CMOS process”, Proceedings International Test Conference 1992, p. 892.Google Scholar
  13. [13]
    Champac, V.H., Figueras, J. and Rubio, A., “Electrical model of the floating gate defect in CMOS IC’s: implications on Iddq testing”, IEEE Transactions on Computer-AidedDesign of Circuits and Systems, vol. 13, no. 3, March 1994, pp. 359–369.CrossRefGoogle Scholar
  14. [14]
    Segura, J. et al., “Quiescent current analysis and experimentation of defective CMOS circuits”, Journal of Electronic Testing: Theory and Application,3, 337–348(1992), Kluwer Academic Publishers.Google Scholar
  15. [15]
    Segura, J. et al., “A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors”, Journal of Electronic Testing: Theory and Application,8, 229–239(1996), Kluwer Academic Publishers.Google Scholar
  16. [16]
    Avizienis, A. and Laprie, J.C., “Dependable computing: from concepts to design diversity”, Proceedings of the IEEE, vol. 74, no. 8, May 1986.Google Scholar
  17. [17]
    Abramovici, M., Breuer, M.A. and Friedman, A.D., Digital Systems Testing and Reliable Design, Computer Science Press, 1990.Google Scholar
  18. [18]
    Abraham, J A and Fuchs, W.K., “Fault and error models for VLSI”, Proceedings of the IEEE, vol. 74, no. 5, May 1986.Google Scholar
  19. [19]
    Breuer, M.A. and Friedman, A.D., “Diagnosis and reliable design of digital systems”, Computer Science-Press, Washington DC 1976.Google Scholar
  20. [20]
    Wadsack, R.L., “Fault modelling and logic simulation of CMOS and MOS integrated circuits”, Bell System Technology Journal, pp. 1449–1474, May-June 1978.Google Scholar
  21. [21]
    Abraham, J.A. and Parker, K.P., “Practical Microprocessor Testing: Open and closed loops approaches”, Proc. COMPCON Spring 1981, pp. 308–311, February 1981.Google Scholar
  22. [22]
    Sharma, M. and Patel, J.H., “Testing of critical paths for delay faults”, Proceedings of the International Test Conference 2001, pp. 634–641.Google Scholar
  23. [23]
    Tyszer, J., “Testing of three-stage switching networks for coupling faults”, IEEE Transactions on Communications, vol. 40. no. 2, Feb. 1992, pp. 413–422.zbMATHCrossRefGoogle Scholar
  24. [24]
    Kuo-Liang Cheng; Ming-Fu Tsai; Cheng-Wen Wu, “Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories”, IEEE Proceedings VLSI Test Symposium 2001, pp. 225–230.Google Scholar
  25. [25]
    Rubio, A.; Itazaki, N.; Xu, X.; Kinoshita, K., “An approach to the analysis and detection of crosstalk faults in digital VLSI circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 3, March 1994, pp. 387–395.CrossRefGoogle Scholar
  26. [26]
    Milne, A.; Taylor, D.; Saunders, J.; Talbot, A.D., “Generation of optimised fault lists for simulation of analogue circuits and test programs”, IEE Proceedings Circuits, Devices and Systems, vol. 146, no. 6, Dec. 1999, pp. 355–360.CrossRefGoogle Scholar
  27. [27]
    Gulati, R.K. and Hawkins, C.F. editors, “IDDQ testing of VLSI circuits”, Kluwer Academic Publishers, 1993.Google Scholar
  28. [28]
    McCluskey, E.J., “Logic Design Principles: with emphasis on testable semicustom circuits”, Prentice Hall International, 1986.Google Scholar
  29. [29]
    Fujiwara, H., “Logic testing and design for testability”, The MIT Press, 1985.Google Scholar
  30. [30]
    Chujen Lin; Haynes, L.; Mandava, P.; Prasad, P., “Automatic BIST design tool for mixed-signal circuits”, AUTOTESTCON ‘88 IEEE Systems Readiness Technology Conference, 1998 IEEE, pp. 97–102.Google Scholar
  31. [31]
    Roth, J.P., “Computer logic, testing and verification”, Computer Science Press, Rockville, Maryland, 1980.zbMATHGoogle Scholar
  32. [32]
    Fujiwara, H. and Shimono, T., “On the acceleration of test pattern generation algorithms”, IEEE Transactions on Computers, vol. C-32, no. 12, pp. 1137–1144, December 1983.CrossRefGoogle Scholar
  33. [33]
    Schulz, M.H. et al., “Improved deterministic test pattern generation with applications to redundancy identification”, IEEE Transactions on Computer-Aided-Design, vol. 8, no. 7, pp. 811–816, July 1989.CrossRefGoogle Scholar
  34. [34]
    Franklin, M.; Saluja, K.K.; Kinoshita, K., “Design of a BIST RAM with row/column pattern sensitive fault detection capability”, Proceedings International Test Conference, 1989, pp. 327–336.Google Scholar
  35. [35]
    Mohammad, M.Gh.; Saluja, K.K.; Yap, A., “Testing flash memories”, Thirteenth International Conference on VLSI Design, 2000, pp. 406–411.Google Scholar
  36. [36]
    Das, D.K.; Bhattacharya, B.B.; Ohtake, S.; Fujiwara, H., “Testable design of sequential circuits with improved fault efficiency”, Fourteenth International Conference on VLSI Design, 2001, pp. 128–133.Google Scholar
  37. [37]
    Heragu, K.; Patel, J.H.; Agrawal, V.D., “A test generator for segment delay faults”, Proceedings, Twelfth International Conference On VLSI Design, 1999, pp. 484–491.Google Scholar
  38. [38]
    Wangning Long; Zhongchen Li; Shiyuan Yang; Yinghua Min, “Memory efficient ATPG for path delay faults”, Proceedings Test Symposium, 1997, pp. 326–331.Google Scholar
  39. [39]
    Kondo, H.; Kwang-Ting Cheng, “An efficient compact test generator for I/sub DDQ/ testing”, Proceedings of the Fifth Asian Test Symposium, 1996, pp. 177–182.Google Scholar
  40. [40]
    Isern, E.; Figueras, J., “Test generation with high coverage for quiescent current test of bridging faults in combinational circuits”, Proceedings International Test Conference, 1993, pp. 73–82.Google Scholar
  41. [41]
    IEEE standard test access port and boundary-scan architecture, IEEE Std 1149.1–2001.Google Scholar
  42. [42]
    IEEE standard for a mixed-signal test bus, IEEE Std 1149. 4–1999, 28 March 2000.Google Scholar
  43. [43]
    Konemann, P., Mucha, J. and Zwiehoff, G., “Built-in logic block observation technique”, Proceedings of the IEEE Test Conference, 1979.Google Scholar
  44. [44]
    Varma, P., Ambler, A.P. and Baker, K., “An analysis of the economics of self test”, Proceedings of the IEEE Test Conference, 1984.Google Scholar
  45. [45]
    Bernard, S.; Azais, F.; Bertrand, Y.; Renovell, M., “Analog BIST generator for ADC testing”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 338–346.Google Scholar
  46. [46]
    Seongwon Kim; Soma, M., “An all-digital built-in self-test for high-speed phase-locked loops”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 2, Feb. 2001, pp. 141–150.CrossRefGoogle Scholar
  47. [47]
    Peralias, E.J.; Huertas, G.; Rueda, A.; Huertas, J.L, “Self-testable pipelined ADC with low hardware overhead”, IEEE Proceedings on VLSI Test Symposium, 2001, pp. 272–277.Google Scholar
  48. [48]
    Turino, J., “Test economics in the 21st century”, IEEE Design and Test of Computers, July-September 1997, pp. 41–44.Google Scholar
  49. [49]
    Ungar, L.Y. and Ambler, T., “Economics of built-in self-test”, IEEE Design and Test of Computers, September-October 2001, pp. 70–79.Google Scholar
  50. [50]
    Zorian, Y., Dey, S. and Rodgers, M.J., “Test of future System-On-Chips”, Proceedings of the International Conference on Computer Aided Design, 2000, pp. 392–398.Google Scholar
  51. [51]
    Lee, T.H. and Wong, S.S., “CMOS RF Integrated Circuits at 5 GHz and Beyond”, Proceedings of the IEEE, vol. 88, no. 10, October 2000, pp. 1560–1571.CrossRefGoogle Scholar
  52. [52]
    Pynn, C.T., “Analyzing Manufacturing Test Costs”, IEEE Design and Test of Computers, July-September 1997, pp. 36–41.Google Scholar
  53. [53]
    Rajsuman, R., “Iddq testing for CMOS VLSI”, Proceedings of the IEEE, vol. 88, no. 4, April 2000, pp. 544–566.CrossRefGoogle Scholar
  54. [54]
    Kundu, S., “Iddq defect detection in deep sub-micron CMOS ICs”, Proceedings of the Asian Test Symposium, 1998, pp. 150–152.Google Scholar
  55. [55]
    Zarrinfar, F. and Rajsuman, R., “Automated Iddq testing from CAD to manufacturing”, Proceedings International Workshop on Iddq testing“, 1995, pp. 48–51.Google Scholar
  56. [56]
    Hawkins, C.F. et al., “Quiescent power supply current measurements for CMOS IC defect detection”, IEEE Transactions on Industrial Electronics, May 1989, pp. 211–218.Google Scholar
  57. [57]
    Cusey, J.P. and Patel, J.H., “BART: A bridging fault test generator for sequential circuits”, Int. Test Conference, 1997, pp. 823–832.Google Scholar
  58. [58]
    Mao, W. et al., Quietest: A quiescent current testing methodology for detecting leakage faults“, Int. Conf. Computer Aided Design, 1990, pp. 280–283.Google Scholar
  59. [59]
    Rullan, M. et al., “Analysis of Issq/Iddq testing implementation and circuit partitioning in CMOS cell based design”, European Design and Test Conference, 1996, pp. 584–588.Google Scholar
  60. [60]
    Sah, C.T., “Characteristics of the Metal-Oxide-Semiconductors Transistors”, IEEE Trans. Electron Devices, ED-11, 324, 1964.Google Scholar
  61. [61]
    Proc. Int. Technology Roadmap for semiconductor, November 1999.Google Scholar
  62. [62]
    Szekely, V.; Rencz, M.; Torok, S.; Courtois, B., “Cooling as a possible way to extend the usability of I/sub DDQ/ testing”, Electronics Letters, Volume: 33 Issue: 25, 4 Dec. 1997, pp. 2117–2118.CrossRefGoogle Scholar
  63. [63]
    Singer, G., “The future of test and DFT”, IEEE Design and Test, July-September 1997, pp. 11–16.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2002

Authors and Affiliations

  • Josep Altet
    • 1
  • Antonio Rubio
    • 1
  1. 1.University Politècnia de CatalunyaSpain

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