Tradeoffs in Digital Binary Adder Design: the effects of floorplanning, number of levels of metals, and supply voltage on performance and area

Abstract

Arithmetic circuits play a crucial role in most complex digital systems today. Virtually all complex digital systems contain arithmetic circuits in their critical paths, and thus the performance of arithmetic circuits can greatly affect the performance of the system as a whole. Likewise the area and power dissipation of arithmetic circuits can be important factors in the determination of the feasibility of the system. Area and power issues appear to be even more important today because circuits are often meant to perform in less than optimum conditions, such as where components are tightly packed and don’t necessarily have large amounts of ventilation. Thus the realization of area- and time-efficient arithmetic circuits is of fundamental importance. This is especially true for adders, which appear in all arithmetic circuits. Unfortunately, establishing what kind of adder is the most appropriate for a specific application is not trivial. In fact, in order to achieve the best area-time trade-off, the designer should analyze the characteristics of several adders. In addition, sometimes the designer is given a fixed portion of the chip area for the circuit, so that there is no flexibility in the shape that the circuit can take. This implies that dependencies of performance and cost on topology and layout constraints should be both taken into account.