Tradeoffs in Digital Binary Adder Design: the effects of floorplanning, number of levels of metals, and supply voltage on performance and area

  • Vitit Kantabutra
  • Stefania Perri
  • Pasquale Corsonello
Part of the Network Theory and Applications book series (NETA, volume 8)


Arithmetic circuits play a crucial role in most complex digital systems today. Virtually all complex digital systems contain arithmetic circuits in their critical paths, and thus the performance of arithmetic circuits can greatly affect the performance of the system as a whole. Likewise the area and power dissipation of arithmetic circuits can be important factors in the determination of the feasibility of the system. Area and power issues appear to be even more important today because circuits are often meant to perform in less than optimum conditions, such as where components are tightly packed and don’t necessarily have large amounts of ventilation. Thus the realization of area- and time-efficient arithmetic circuits is of fundamental importance. This is especially true for adders, which appear in all arithmetic circuits. Unfortunately, establishing what kind of adder is the most appropriate for a specific application is not trivial. In fact, in order to achieve the best area-time trade-off, the designer should analyze the characteristics of several adders. In addition, sometimes the designer is given a fixed portion of the chip area for the circuit, so that there is no flexibility in the shape that the circuit can take. This implies that dependencies of performance and cost on topology and layout constraints should be both taken into account.


Supply Voltage Full Adder Arithmetic Circuit Circuit Delay Critical Delay Path 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    A. P. Chandrakasan, S. Sheng, R. Brodersen “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, Vol.27, n 4, April 1992, pp.473484.Google Scholar
  2. [2]
    H. Esbensen and E. S. Kuh. “Explorer: An interactive floorplanner for design space exploration,” EuroDAC-96, pp. 356–361, 1996.Google Scholar
  3. [3]
    V. Kantabutra, “Designing Optimum Carry-Skip Adders,” IEEE Trans. Computers, June, 1993.Google Scholar
  4. [4]
    V. Kantabutra, P. Corsonello, and S. Perri, “Fast, low-cost adders using carry-strength signals,” INVITED PAPER, SSGRR 2000, Computer and E-Business Conference, L’Aquila, Italy.Google Scholar
  5. [6]
    M. Mal-gala and N. G. Durdle, “Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation–a comparative study,” IEEE J. Solid State Circuits, Vol.33, n10, October 1998, pp. 1580–1585Google Scholar
  6. [7]
    C. Nagendra, R. M. Owens, and M. J. Irwin, “Power-delay characteristics of CMOS adders,” IEEE Trans. VLSI systems, Vol.2, n3, September 1994, pp. 377–381CrossRefGoogle Scholar
  7. [8]
    V. Narayananan, D. LaPotin, R. Gupta, and G. Vijayan, “Pepper–a timing driven early floorplanner,” Proc. Int’l Conf. Computer Design, pp. 230–235, 1995.Google Scholar
  8. [9]
    S. M. Sait, H. Youssef, S. Tanvir, and M. S. T. Benten. “Timing influenced general-cell genetic floorplanner,” Proc. ASP-DAC ‘85; CHDL ‘85; VLSI ‘85; IFIP Int’l Conf. Hardware Description Languages; IFIP Int’l Conf. on VLSI, Asian and South Pacific, pp. 135–140, 1995.Google Scholar
  9. [10]
    N. A. Sherwani, Algorithms for VLSI Physical Design Automation, 3rd ed., Norwell, MA, Kluwer Academic Publisher, 1999, p. 193.zbMATHGoogle Scholar
  10. [11]
    W. Wolf Modern VLSI design - System on silicon, 2nd ed., Prentice Hall, Upper Saddle River NJ, USA, 1998Google Scholar
  11. [12]
    H. Youssef, S. M. Sait, and K. J. Al-Farra, “Timing influenced force-directed floorplanning,” Proc. EURO-DAC, pp. 156–161, 1995.Google Scholar
  12. [13]
    T. Yamanouchi, K. Tamakashi, and T. Kambe. “Hybrid floorplanning based on partial clustering and module restructuring,” IEEE/ACM Int’l Conf.,1995, pp. 478–483; ICCAD Digest of Tech. Papers, 1996;Google Scholar
  13. [14]
    R. Zimmerman and W. Fichtner “Low-power logic style: CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits, Vol.32, n7, July 1997, pp. 1079–1090.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Vitit Kantabutra
    • 1
  • Stefania Perri
    • 2
  • Pasquale Corsonello
    • 3
  1. 1.College of EngineeringIdaho State UniversityPocatelloUSA
  2. 2.Department of Electronics, Computer Science and SystemsUniversity of CalabriaRende(CS)Italy
  3. 3.Department of Informatics, Mathematics, Electronics, and TransportationUniversity of Reggio CalabriaReggio CalabriaItaly

Personalised recommendations