Techniques for Timing-Driven Routing

  • John Lillis
Part of the Network Theory and Applications book series (NETA, volume 8)


With every new generation of fabrication technology for VLSI we see an increased influence of interconnect on system performance. With device scaling interconnect parasitics become increasingly influential. Issues such as layer assignment, via resistance, wire-to-wire coupling capacitance, wire width and signal buffering now play major roles in determining signal delay.


Priority Queue Path Delay Coupling Capacitance Source Vertex Delay Estimator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • John Lillis
    • 1
  1. 1.Department of Computer ScienceUniversity of IllinoisChicagoUSA

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