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Integrated Floorplanning and Interconnect Planning

  • Hung-Ming Chen
  • Martin D. F. Wong
  • Hai Zhou
  • Fung-Yu Young
  • Hannah H. Yang
  • Naveed Sherwani
Part of the Network Theory and Applications book series (NETA, volume 8)

Abstract

When VLSI technology enters the deep sub-micron era, communication between different components is significantly increased. Interconnect delay also becomes the dominant factor in total circuit delay. All these make it necessary to start interconect planning as early as possible. In this chapter, we propose a method to combine interconnect planning with floorplanning. Our approach is based on the Wong-Liu floorplanning algorithm. When the positions, orientations, and shapes of the cells are decided, the pin positions and routing of the interconnects are decided as well. We use a multi-stage simulated annealing approach in which different interconnect planning methods are used in different ranges of temperatures to reduce running time. A temperature adjustment scheme is designed to give smooth transistions between different stages of simulated annealing. Experimental results show that our approach performs well.

Keywords

Cost Function Simulated Annealing Temperature Adjustment Polish Expression Global Interconnect 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Hung-Ming Chen
    • 1
  • Martin D. F. Wong
    • 1
  • Hai Zhou
    • 2
  • Fung-Yu Young
    • 3
  • Hannah H. Yang
    • 4
  • Naveed Sherwani
    • 4
  1. 1.Department of Computer SciencesThe University of Texas at AustinAustinUSA
  2. 2.Advanced Technology GroupSynopsys, Inc.Mountain ViewUSA
  3. 3.Department of Computer Science and EngineeringThe Chinese University of Hong KongShatin, Hong KongChina
  4. 4.Strategic CAD LabsIntel CorporationHillsboroUSA

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