An Asynchronous Viterbi Decoder

Abstract

Viterbi decoders are used for decoding data encoded using convolutional forward error correcting codes. Such codes are used in a large proportion of digital transmission and digital recording systems because, even when the transmitted signal is subjected to significant noise, the decoder is still able efficiently to determine the most likely transmitted data.

This chapter descibes a novel Viterbi decoder aimed at being power efficient through adopting an asynchronous approach. The new design is based upon serial unary arithmetic for the computation and storage of the metrics required; this arithmetic replaces the add-compare-select parallel arithmetic performed by conventional synchronous systems. Like all Viterbi decoders, a history of computational results is built up over many data bits to determine the data most likely to have been transmitted at an earlier time. The identification of a starting point to this tracing operation allows the storage requirement to be greatly reduced compared with that in conventional decoders where the starting point is random. Furthermore, asynchronous operation in the system described enables multiple, independent, concurrent tracing operations to be performed which are decoupled from the placing of new data in the history memory.

The Viterbi design work was supported by the EPSRC/MoD PowerPack project GR/L27930 and the EU PREST project EP25242, and this support is gratefully acknowledged.