Programmable DSP Based Implementation

  • Manesh Mehendale
  • Sunil D. Sherlekar


A programmable DSP is a processor customized to implement digital signal processing algorithms efficiently. The customization is based on the following characteristics of DSP algorithms:
  • Compute Intensive: Most DSP kernels are compute intensive with weighted-sum being the core computation. A programmable DSP hence incorporates a dedicated hardwired multiplier and its datapath supports single cycle multiply-accumulate (MAC) operation.

  • Data Intensive: In most DSP kernels, each multiply operation of the weight-sum computation is performed on a new set of coefficient and data values. A programmable DSP is hence pipelined with an operand read stage before the execute stage, has an address generator unit that operates in parallel with the execute datapath and uses a Harvard architecture with multiple busses to program and data memory.

  • Repetitive: DSP algorithms are repetitive both at micro-level (e.g. Multiply-accumulate operation repeated N times during an N-term weighted-sum computation) and at macro-level (e.g. kernels such as filtering repeated every time a new data sample is read). A DSP architecture hence uses special instructions (such as RPT MAC) and control mechanisms to support zero overhead looping.


Power Dissipation Signal Flow Graph Stopband Attenuation Passband Ripple Adjacent Signal 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2001

Authors and Affiliations

  • Manesh Mehendale
    • 1
  • Sunil D. Sherlekar
    • 2
  1. 1.Texas Instruments (India), Ltd.USA
  2. 2.Silicon Automation Systems Ltd.USA

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