Abstract
A programmable DSP is a processor customized to implement digital signal processing algorithms efficiently. The customization is based on the following characteristics of DSP algorithms:
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Compute Intensive: Most DSP kernels are compute intensive with weighted-sum being the core computation. A programmable DSP hence incorporates a dedicated hardwired multiplier and its datapath supports single cycle multiply-accumulate (MAC) operation.
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Data Intensive: In most DSP kernels, each multiply operation of the weight-sum computation is performed on a new set of coefficient and data values. A programmable DSP is hence pipelined with an operand read stage before the execute stage, has an address generator unit that operates in parallel with the execute datapath and uses a Harvard architecture with multiple busses to program and data memory.
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Repetitive: DSP algorithms are repetitive both at micro-level (e.g. Multiply-accumulate operation repeated N times during an N-term weighted-sum computation) and at macro-level (e.g. kernels such as filtering repeated every time a new data sample is read). A DSP architecture hence uses special instructions (such as RPT MAC) and control mechanisms to support zero overhead looping.
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© 2001 Springer Science+Business Media New York
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Mehendale, M., Sherlekar, S.D. (2001). Programmable DSP Based Implementation. In: VLSI Synthesis of DSP Kernels. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3355-6_2
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DOI: https://doi.org/10.1007/978-1-4757-3355-6_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-4904-2
Online ISBN: 978-1-4757-3355-6
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