VHDL-AMS, a unified language to describe Multi-Domain, Mixed-Signal designs. Mechatronic applications

Abstract

In this paper, we present some methodology for the use of VHDL-AMS on mechatronic applications. The methodology is highlighting that VHDL-AMS is a unified Mixed-Signal language including VHDL digital features to describe pure analog designs. Without reducing the scope of the language, the subset proposed with this methodology uses at maximum the potential of classical mechanical, hydraulic and electrical simulators. Descriptions and simulation results are also presented to show the usability of such language for mechatronic applications.