VHDL Dynamic Loop Synthesis

Abstract

VHDL [1, 2, 3, 4] dynamic loop synthesis is a difficult problem, in the general case. It is the reason why no CAD tool implement them.. But in fact, it is possible, with specific conditions, to resolve this problem in the particular case of logic synthesis because in this context, the size of loops is limited and this loops can be explored exhaustively to calculate their maximal size. This first step provides a solution to combinational synthesis of loops. Sequential synthesis is a second step in order to explore many multi-cycles solutions. A loop of N iterations can be treated in 1 to N clock cycles by reducing the combinational loop and introducing a counter of cycles. Automatic pipeline synthesis is the last step aimed to improve the throughput of the synthesised component. Several tools have introduced such possibilities in order to explore architectural solutions and compromises between full combinational, full sequential, pipelined or not, solutions [5], [6], [7]. The aim of this paper is to present the two first steps of loop synthesis in the two first parts. The last part will illustrate this approach with a simple algorithm