ECL: A Specification Environment for System-Level Design
We propose a new specification environment for system-level design called ECL. It combines the Esterel and C languages to provide a more versatile means for specifying heterogeneous designs. It can be viewed as the addition to C of explicit constructs from Esterel for concurrency and pre-emption, and thus makes these operations easier to specify and more apparent. An ECL specification is compiled into a reactive part (an extended finite state machine representing most of the ECL program), and a pure data looping part. The first can be robustly estimated and synthesized to hardware or software, while the second is implemented in software as specified. ECL is a good candidate for specification of new behavior in system-level design tools such as Cadence’s Cierto VCC tool. ECL is especially targeted for specification of control protocols between data-computing behavioral blocks.
KeywordsFinite State Machine Reactive Part Clock Tick Extended Finite State Machine Property Verification
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- For more information on Cadence’s Cierto VCC product, visit http://http://www.cadence.com/technology/hwsw/ciertovcc.
- The Java version of the ECL compiler has recently become available. Visit http://www.cadence.com/programs/na/research.shtml and follow the ECL project link.
- F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach. Kluwer Academic Publishers, 1997.Google Scholar
- G. Berry. The Foundations of Esterel. 1998. To appear.Google Scholar
- E. Sentovich and L. Luciano. ECL: A Specification Environment for System-Level Design. In 36nd DAC, pages 511–516, June 1999.Google Scholar