ECL: A Specification Environment for System-Level Design

  • Gérard Berry
  • Ed Harcourt
  • Luciano Lavagno
  • Ellen Sentovich


We propose a new specification environment for system-level design called ECL. It combines the Esterel and C languages to provide a more versatile means for specifying heterogeneous designs. It can be viewed as the addition to C of explicit constructs from Esterel for concurrency and pre-emption, and thus makes these operations easier to specify and more apparent. An ECL specification is compiled into a reactive part (an extended finite state machine representing most of the ECL program), and a pure data looping part. The first can be robustly estimated and synthesized to hardware or software, while the second is implemented in software as specified. ECL is a good candidate for specification of new behavior in system-level design tools such as Cadence’s Cierto VCC tool[1]. ECL is especially targeted for specification of control protocols between data-computing behavioral blocks.


Finite State Machine Reactive Part Clock Tick Extended Finite State Machine Property Verification 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    For more information on Cadence’s Cierto VCC product, visit http://
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    The Java version of the ECL compiler has recently become available. Visit and follow the ECL project link.
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    G. Berry. The Foundations of Esterel. 1998. To appear.Google Scholar
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    E. Sentovich and L. Luciano. ECL: A Specification Environment for System-Level Design. In 36nd DAC, pages 511–516, June 1999.Google Scholar

Copyright information

© Springer Science+Business Media New York 2001

Authors and Affiliations

  • Gérard Berry
  • Ed Harcourt
  • Luciano Lavagno
  • Ellen Sentovich

There are no affiliations available

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