Quantum Effects and Devices

  • Yasuhisa Omura


To find a physical study that considers quantum effect devices at the fundamental level, we have to go back to the tunneling diode by L. Esaki[1]. It is symbolic that he used Ge, which is one of the covalent semiconductors. It is also interesting that silicon materials are attracting attention of many researchers today.


Gate Voltage Tunnel Junction Silicon Layer Anode Voltage Coulomb Blockade 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    L. Esaki, L“New phenomenon in narrow germanium p-n junction,” Phys. Rev., vol. 109, p. 603, 1958.CrossRefGoogle Scholar
  2. 2.
    R. Tsu and L. Esaki, Tunneling in a finite superlattice,” Appl. Phys. Lett., vol. 22, p. 562, 1973.CrossRefGoogle Scholar
  3. 3.
    A.C. Warren, D.A. Antoniadis, H.I. Smith, and J. Melngailis, “Surface superlattice formation in Silicon inversion layers using 0.2-μm period grating-gate electrodes,” IEEE Electron device Lett., vol. EDL-6, p. 294, 1985.CrossRefGoogle Scholar
  4. 4.
    A.C. Warren, D.A. Antoniadis and H.I. Smith “Quasi one-dimensional conduction in multiple, Parallel Inversion Lines,” Phys. Rev. Lett., vol. 56, p. 1858, 1986.CrossRefGoogle Scholar
  5. 5.
    H. Matsuoka, T. Ichiguchi, T. Yoshimura and E. Takeda, “Mobility modulation in a quasi-one-dimensional Si-MOSFET with a dual-gate structure,” IEEE Electron Device Lett., vol. 13, p. 20, 1992.CrossRefGoogle Scholar
  6. 6.
    H. Matsuoka, T. Yoshimura, T. Ichiguchi and E. Takeda, “Coulomb blockade in the inversion layer of a Si metal-oxide-semiconductor field-effect transistor with a dual-gate structure,” Appl. Phys. Lett., vol. 64, p. 586, 1994.CrossRefGoogle Scholar
  7. 7.
    Y. Ono, Y. Takahashi, S. Horiguchi, K. Murase and M. Tabe, “Electron tunneling from the edge of thin single-crystal Si layers through SiO2 film,” J. Appl. Phys. vol. 80, p. 4450, 1996.CrossRefGoogle Scholar
  8. 8.
    Y. Omura, “Quantum effect devices on SOI substrates with an ultrathin silicon layer,” from Proc. of NATO Advanced Research Workshop on Perspective, Science and Technology for Novel Silicon on Insulator Devices (Kluwer Academic Publisher, 1999) p. 257.Google Scholar
  9. 9.
    E. Merzbacher, “Quantum Mechanics,” (3rd ed., Wiley, 1998), chap. 5–7.Google Scholar
  10. 10.
    A. Hartstein, “Quantum interference in ultrashort channel length silicon metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 59, p. 2028, 1991.CrossRefGoogle Scholar
  11. 11.
    L.L. Chang, L. Esaki and R. Tsu, “Resonant tunneling in semiconductor double barriers,” Appl. Phys. Lett., vol. 24, p. 593, 1974.CrossRefGoogle Scholar
  12. 12.
    F. Capasso, S. Sen, L.M. Lunardi and A.Y. Cho, “Quantum Transistors and circuits Break through the barriers,” IEEE Circuits and Device, vol. 7, p. 18, 1991.CrossRefGoogle Scholar
  13. 13.
    K. Yuki, Y. Hirai, K. Morimoto, K. Inoue, M. Niwa and J. Yasui, “Fabrication of Novel Si Double-Barrier Structures,” Jpn. J. Appl. Phys., vol. 34, p. 860, 1995.CrossRefGoogle Scholar
  14. 14.
    K.F. Brennan, “The physics of semiconductors,” Cambridge University press, 1999, p. 688.Google Scholar
  15. 15.
    Y. Fu and M. Willander, “Physical models of semiconductor quantum devices,” Kluwer Academic Publishers, 1999.Google Scholar
  16. 16.
    J.P. Colinge, X. Baie and V. Bayot, “Evidence of Two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices,” IEEE Electron Device Lett., vol. 15, pp. 193–195, 1994.CrossRefGoogle Scholar
  17. 17.
    Y. Omura and M. Nagase, “Low-Temperature Drain Current Characteristics in Sub-10-nm-Thick SOI nMOSFET’s on SIMOX substrates,” Jpn. J. Appl. Phys., vol. 34, p. 812, 1995.CrossRefGoogle Scholar
  18. 18.
    Y. Omura, K. Kurihara, Y. takahashi, T. Ishiyama, Y. Nakajima and K. Izumi, “50-nm channel nMOSFET/SIMOX with an ultrathin 2-or 6-nm thick silicon layer and their significant features of operations,” IEEE Electron Device Lett., vol. 18, p. 190, 1997.CrossRefGoogle Scholar
  19. 19.
    T. Takahashi and M. Miura-Matausch, and Y. Omura, “Transconductance oscillations in metal-oxide-semiconductor field-effect transistors with thin silicon-on-insulator originated by quantized energy levels,” Appl. Phys. Lett., vol. 75, p. 1458, 1999.CrossRefGoogle Scholar
  20. 20.
    Y. Omura, Two-dimensionally confined injection phenomena in sub-10-nm-thick SOI insulated-gate pn-junction devices,” Ext. Abstr. of the 1995 Int. Conf. on Solid State Devices and Materials, p. 563Google Scholar
  21. 21.
    Y. Omura, “Two-dimensionally confined injection phenomena at low temperatures in sub-10-nm-thick SOI insulated-gate p-n-junction devices,” IEEE Trans. on Electron Devices, vol. 43, p. 436, 1996.CrossRefGoogle Scholar
  22. 22.
    M. Nagase, T. Ishiyama and K. Murase, “Surface Morphology of SIMOX-Si Layers Characterized Using Atomic Force Microscopy,” in Proc. of the 6th Int. Symp. on SOI Technol. (The Electrochemical Society, San Francisco, 1994), p. 191.Google Scholar
  23. 23.
    Y. Nakajima, Y. Takahashi, S. Horiguchi, K. Iwadate, H. Namatsu, K. Kurihara and M. Tabe, “Quantized conductance of a silicon wire fabricated by separation-by-implanted-oxygentechnology,” Jpn. J. Appl. Phys., vol. 34, p. 1309, 1995.CrossRefGoogle Scholar
  24. 24.
    S. Horiguchi, Y. Nakajima, Y. Takahashi and M. Tabe, “Energy eigenvalues and quantized conductance values of electrons in Si quantum wires on 100 plane,” Jpn. J. Appl. Phys., vol. 34, p. 5489, 1995.CrossRefGoogle Scholar
  25. 25.
    G. Timp, J. Bude, K.K. Bourdelle, J. Garno, A. Ghetti, H. Gossman, M. Green, G. Forsyth, Y. Kim, R. Kleiman, H. Klemens, A. Kornblit, C. Lochstampfor, W. Mandfield, S. Moccio, T. Sorsch, D.M. Tennant, W. Timp, R. Tung, “The ballistic Nanotransistor,” 1999 IEEE Int. Electron Devices Meeting (Washington, 1999), p. 55.Google Scholar
  26. 26.
    T. Uemura and T. Baba, “First observation of negative differential resistance in surface tunnel transistors,” Jpn. J. Appl. Phys., vol. 33, p. L207, 1994.CrossRefGoogle Scholar
  27. 27.
    Y. Omura, “Distinclt Two-dimensional Carrier Injection Phenomena in Extremely Thin-SOI Insulated-Gate pn-Junction Devices: Prospect of new device applications,” Abstr. Workbook of 9th Int. Conf. on Superlattices, Microstructures and Microstructures, vol. 24, p. 83, 1998.CrossRefGoogle Scholar
  28. 28.
    Y. Omura, “Negative conductance properties in Extremely thin Silicon-on-insulator (SOI) Insulated-gate pn-Junction Devices SOI Surface Tunnel Transistors),” Jpn. J. Appl. Phys. vol. 11 A, p. L1401, 1996.CrossRefGoogle Scholar
  29. 29.
    J. Koga and A. Toriumi, “Negative differential conductance at room temperature vol. 70, p. 2138, 1997.Google Scholar
  30. 30.
    Y. Omura, “A Lateral Unidirectional, Bipolar-Type, Insulated-Gate Transistor-A New Device,” Applied Phys. Lett., vol. 40, p. 528, 1982.CrossRefGoogle Scholar
  31. 31.
    J. Bardeen, “Tunneling from a many-particle point of view,” Phys. Rev. Lett., vol. 6, p. 57, 1961.CrossRefGoogle Scholar
  32. 32.
    Y. Omura, “Features of indirect-band-to-band tunneling in an insulated-gate lateral pn junction device on a SIMOX substrate with an ultrathin 10-nm-thick silicon layer”, J. Phys. IV, vol. 8, p. Pr3–63, 1998 (Proc. of 3rd European Workshop on Low-Temperature Electronics, Italy).Google Scholar
  33. 33.
    S. Datta, M.R. Melloch, S. Bandyopadhyay, and M.S. Lundstrom, “Proposed structure for large quantum interference effects,” Appl. Phys. Lett., vol. 48, p. 487, 1986.CrossRefGoogle Scholar
  34. 34.
    S. Datta and S. Bandyopadhyay, “Aharonov-Bohmeffect in semiconductor microstructures,” Phys. Rev. Lett., vol. 58, p. 717, 1987.CrossRefGoogle Scholar
  35. 35.
    D.C. Miller, R.K. Lake, S. Datta, M.S. Lundstrom, M.R. Melloch, and R. Reifenberger, Nanostructure Physics and Fabrication (Academic Press, New York, 1992) P. 165.Google Scholar
  36. 36.
    H. Sakaki, “Scattering suppression and high-mobility effect of size-quantized electrons in ultrafine semiconductor wire structures,” Jpn. J. Appl. Phys., vol. 19, p. L735, 1980.CrossRefGoogle Scholar
  37. 37.
    T. Ando, A.B. Fowler and F. Stern, “Electronic properties of two-dimensional systems,” Rev. Mod. Phys., vol. 54, p. 437, 1982.CrossRefGoogle Scholar
  38. 38.
    Y. Takahashi, M. Nagase, H. Namatsu, K. Kurihara, K. Iwadate, Y. Nakajima, S. Horiguchi, K. Murase and M. Tabe, “Conductance oscillation of a Si Single Electron transistor at room temperature,” Ext. Abstr. IEEE Int. Electron Devices Meeting (Washington. D.C., 1994) p. 938.Google Scholar
  39. 39.
    K.K. Likharev, “Single-electron transistors: electronic analogs of the DC squids,” IEEE Trans. Magn., vol. 23, p. 1142, 1987.CrossRefGoogle Scholar
  40. 40.
    J.R. Tucker, “Complementary digital logic based on the Coulomb blockade,” J. Appl. Phys., vol. 72, p. 4399, 1992.CrossRefGoogle Scholar
  41. 41.
    K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, T. Kure, and K. Seki, “Status of single-electron memories,” Ext. Abstr. 1998 IEEE Int. Electron Device Meeting(San Francisco, 1998), p. 107.Google Scholar
  42. 42.
    Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara and K. Murase, “A multi-gate single-electron Transistor and its application to an exclusive-OR gate,” Ext. bstr. of 1998 IEEE Int. Electron Devices Meeting(San Francisco, 1998), p. 367.Google Scholar
  43. 43.
    Y. Ono, Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K. Kurihara and K. Murase, “Si complementary single-electron inverter,” Ext. Abstr. of 1999 IEEE Int. Electron Devices Meeting(Washington, 1999), p. 367.Google Scholar
  44. 44.
    N. Takahashi, H. Ishikuro and T. Hiramoto, “A Directional current switch using silicon single electron transistors controlled by charge injection into silicon nano-crystal floating dots,” Ext. Abstr. of 1999 IEEE Int. Electron Devices Meeting(Washington, 1999), p. 371.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Yasuhisa Omura
    • 1
  1. 1.Departement of Electronics, Faculty of EngineeringKansai UniversitySuita, OsakaJapan

Personalised recommendations