Device Physics and Electrical Performance of Bulk Silicon Mosfets

  • Gérard Ghibaudo
  • Francis Balestra


Low temperature operation of Silicon CMOS transistors may be considered as a promising way to improve the device and circuit performances. The temperature reduction allows a substantial increase of the carrier mobility and saturation velocity, better turn-on capabilities, latch-up immunity, reduction in activated degradation processes, lower power consumption, decrease of leakage current, reduced thermal noise, increased thermal conductivity, etc [1–12]. Nevertheless, the low temperature operation leads to some problems and difficulties related to specific cryogenic conditions. For instance, the impurity freeze-out, kink phenomenon, series resistance effects, transient behavior, changes in mobility laws make it difficult the physical understanding and modeling of MOS devices operated at low temperature (4.2–300K).


Inversion Layer IEEE Electron Device Gate Current Drain Bias Drain Induce Barrier Lowering 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    F. Fang, A. B. Fowler, “Hot electron effect and saturation velocity in silicon inversion layers”, J. Appl. Phys., 41, 1825 (1970).CrossRefGoogle Scholar
  2. [2]
    see special issue of IEEE Trans Electron Dev., 36 (1986).Google Scholar
  3. [3]
    R. K. Kirschman, “Cold electronics: an overview”, Cryogenics, 25, 115 (1985).CrossRefGoogle Scholar
  4. [4]
    N. S. Saks, A. Nordbryn, “Time dependence of depletion region formation in phosphorus doped silicon MOS devices at cryogenic temperatures”, J. Appl. Phys., 50, 6962 (1979).CrossRefGoogle Scholar
  5. [5]
    S. Tewksbury, “Transient response of n-channel metal-oxide-semiconductor field effect transistors during turn-on at 10–25K”, J. Appl. Phys., 53, 3865 (1982).CrossRefGoogle Scholar
  6. [6]
    J. C. Woo, J. D. Plummer, “Short channel effect in MOSFETs at liquid nitrogen temperature”, IEEE Trans Electron Dev., ED-33, 1012 (1986).CrossRefGoogle Scholar
  7. [7]
    C. Huang, S. Gildenblat, “Measurements and modelling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60–300K”, IEEE Trans Electron Dev., ED-37, 1289 (1990).CrossRefGoogle Scholar
  8. [8]
    F. Balestra, L. Audaire, C. Lucas, “Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperature”, Solid State Electron, 30, 321 (1987).CrossRefGoogle Scholar
  9. [9]
    E. Simoen, B. Dierickx, L. Warmerdam, J. Vermeiren, C. Claeys, “Freeze-out effects on NMOS transistor characteristics at 4.2K”, IEEE Trans Electron Dev., ED-36, 1155 (1989).CrossRefGoogle Scholar
  10. [10]
    I. M. Hafez, G. Ghibaudo, F. Balestra, “Reduction of kink effect in short channel MOS transistors”, IEEE Electron Device Lett., EDL-11, 120 (1990).CrossRefGoogle Scholar
  11. [11]
    F. Balestra, G. Ghibaudo, “Brief review of the MOS device physics for low temperature electronics”, Solid State Electron, 37, 1967 (1994).CrossRefGoogle Scholar
  12. [12]
    W. F. Clark, B. El-Kareh, R. Pires, S. L. Titcomb, R. L. Anderson, “Low temperature CMOS: A brief review”, IEEE Trans Components Hybrids and Manufacturing Technology, CHMT-15, 397 (1992).CrossRefGoogle Scholar
  13. [13]
    T. Ando, A. Fowler and F. Stern, “Electronic properties of two-dimensional systems”, Rev. Mod. Phys., 54, 437 (1982).CrossRefGoogle Scholar
  14. [14]
    F. Stern, “Quantum properties of surface space-charge layers”, CRC Critical Rev. Solid-St. Sci., 5, 499 (1974).Google Scholar
  15. [15]
    C. Moglestue, “Self-consistent calculation of electron and hole inversion charges at silicon-silicon dioxide interfaces”, J. Appl. Phys., 59, 3175 (1986).CrossRefGoogle Scholar
  16. [16]
    G. Ghibaudo, “Transport in the inversion layer of a MOS transistor: use of Kubo-Greenwood formalism”, J. Phys., C 19, 767 (1985).Google Scholar
  17. [17]
    J. Pals, “Measurements of the surface quantization in silicon n-and p-type inversion layers at temperatures above 25 K”, Phys. Rev., B7, 754 (1973).Google Scholar
  18. [18]
    K. Von Klitzing, G. Dorda and M. Pepper, “New method for high-accuracy determination of the fine-structure constant based on quantized Hall resistance”, Phys. Rev. Lett., 45, 494 (1980).CrossRefGoogle Scholar
  19. [19]
    M. J. Van Dort, P. H. Woerlee A. J. Walker, C. A. H. Juffermans and H. Lifka, “Effects of high normal electric fields in deep submicron MOSFET’s”, Microelectron. Eng., 15, 551 (1991).CrossRefGoogle Scholar
  20. [20]
    C. T. Sah, T. Ning and L. Tschopp, “The scattering of electrons by surface oxide charges and by lattice vibrations at the silicon-silicon dioxide interface”, Surf. Sciences, 32, 561 (1972).CrossRefGoogle Scholar
  21. [21]
    S. Kawaji, “The two-dimensional lattice scattering mobility in a semiconductor inversion layer”, J. Phys. Soc. Japan, 27, 906 (1969).CrossRefGoogle Scholar
  22. [22]
    F. Stern, “Calculated temperature dependence of mobility in silicon inversion layers”, Phys. Rev. Lett., 44, 1469 (1980).CrossRefGoogle Scholar
  23. [23]
    G. Ghibaudo and F. Balestra, “Modelling of ohmic MOSFET operation at very low temperature”, Solid St. Electron., 31, 105 (1988).CrossRefGoogle Scholar
  24. [24]
    F. Fang and A. Fowler, “Transport properties of electrons in inverted silicon surfaces”, Phys. Rev. B3, 619 (1968).CrossRefGoogle Scholar
  25. [25]
    T. Sato, Y. Takeishi and H. Hara, “Mobility anisotropy of electrons in inversion layers on oxidized silicon surfaces”, Phys. Rev., B4, 1950 (1971).Google Scholar
  26. [26]
    A. Emrani, Ph. D. Thesis dissertation, INP Grenoble (1992).Google Scholar
  27. [27]
    S. C. Sun, J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces”, IEEE Trans Electron Dev., ED-27, 1497 (1980).CrossRefGoogle Scholar
  28. [28]
    A. Hairapetian, D. Gitlin, C. R. Viswanathan, “Low temperature mobility measurements in CMOS devices. ”, IEEE Trans Electron Dev., ED-36, 1448 (1989).CrossRefGoogle Scholar
  29. [29]
    A. Emrani, F. Balestra, G. Ghibaudo, “Generalized mobility law for drain current modeling in Si MOS transistors from liquid helium to room temperature”, IEEE Trans Electron Dev., ED-40, 564 (1993).CrossRefGoogle Scholar
  30. [30]
    A. Emrani, F. Balestra, G. Ghibaudo, “On the understanding of electron and hole mobilitiy models from room to liquid helium temperatures”, Solid State Electron, 37, 1723 (1994).CrossRefGoogle Scholar
  31. [31]
    K. Rais, F. Balestra, G. Ghibaudo, “On the high electric field mobility behavior in Si MOSFETs from room to liquid helium temperature”, Phys. Status Solidi (a), 145, 217 (1994).CrossRefGoogle Scholar
  32. [32]
    K. Rais, F. Balestra, G. Ghibaudo, “Surface roughness mobility model for silicon MOS transistor”, Phys. Status Solidi (a), 146, 853 (1994).CrossRefGoogle Scholar
  33. [33]
    A. Emrani, G. Ghibaudo, F. Balestra, “On the universal electric field dependence of the electron and hole effective mobility in MOS inversion layers”, Solid State Electron, 37, 111 (1994).CrossRefGoogle Scholar
  34. [34]
    A. Modelli, S. Manzini, “High drift velocity of electrons in silicon inversion layers”, Solid State Electron, 31, 99 (1988).CrossRefGoogle Scholar
  35. [35]
    K. Rais, G. Ghibaudo, F. Balestra, M. Dutoit, “Study of saturation velocity overshoot in deep submicron silicon MOSFETs from liquid helium up to room temperature”, J. Phys. IV, C6, p. 19 (1994).Google Scholar
  36. [36]
    G. Shahidi, D. Antoniadis, H. Smith, “Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers”, IEEE Electron Device Lett., EDL-9, 94 (1988).CrossRefGoogle Scholar
  37. [37]
    S. Laux, M. Fischietti, “Monte Carlo simulation of submicrometer Si-n MOSFETs at 77 and 300K”, IEEE Electron device Lett., EDL-9, 467 (1988).CrossRefGoogle Scholar
  38. [38]
    J. B. Roldan, F. Gamiz, J. A. Lopez-Villanueva, J. E. Carceller, « Modeling effects of electron-velocity overshoot in a MOSFET », IEEE Trans Electron Devices., ED-44, 841 (1997).CrossRefGoogle Scholar
  39. [39]
    J. B. Roldan, F. Gamiz, J. A. Lopez-Villanueva, P. Cartujo, J. E. Carceller, « A model for the drain current of deep submicrometer MOSFETs including electron-velocity overshoot », IEEE Trans Electron Devices., ED-45, 2249 (1998).CrossRefGoogle Scholar
  40. [40]
    I. M. Hafez, G. Ghibaudo, F. Balestra, M. Haond, “Impact of LDD structures on the operation of silicon MOSFETs at low temperature”, Solid State Electron, 38, 419 (1995).CrossRefGoogle Scholar
  41. [41]
    I. M. Hafez, G. Ghibaudo, F. Balestra, “Analysis of the kink effect in MOS transistors”, IEEE Trans Electron Dev., ED-37, 818 (1990).CrossRefGoogle Scholar
  42. [42]
    D. Foty, “Impurity ionization in MOSFETs at very low temperature”, Cryogenics, 30, 1056 (1990).CrossRefGoogle Scholar
  43. [43]
    E. Simoen, B. Dierickx, L. Deferm, C. Claeys, G. Declerck, “The charge transport in a silicon resistor at liquid helium temperature”, J. Appl. Phys., 68, 4091 (1990).CrossRefGoogle Scholar
  44. [44]
    S. M. Sze, Physics of Semiconductor Devices (New York: Wiley, 1981).Google Scholar
  45. [45]
    N. Arora and M. S. Sharma, “Modeling the anomalous threshold voltage behavior of submicrometer MOSFET’s”, IEEE Electron Device Letters, EDL-13, 92 (1992).CrossRefGoogle Scholar
  46. [46]
    C. S. Rafferty, H. H. Vuong, S. A. Eshraghi, M. D. Giles, M. R. Pinto, S. J. Hillenius, “Explanation of reverse short channel effect by defect gradients”, IEDM Technical Digest, p. 311 (1993).Google Scholar
  47. [47]
    H. Jacobs, A. V. Schwerin, D. Scharfetter, F. Lau, “MOSFET reverse short channel effect due to silicon interstitial capture in gate oxide”, IEDM Technical Digest, p. 307 (1993).Google Scholar
  48. [48]
    A. Kalnitsky, R. Frijns, C. Mallardeau, E. Daemen, M. Bonis, M. Varrot, M. T. Basso, R. Penning de Vries, “Suppression of the Vt roll-up effect in sub-micron NMOST”, Proc. ESSDERC 94, p. 377.Google Scholar
  49. [49]
    M. Nishida and H. Onodera, “An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted n-channel MOSFETs”, IEEE Trans Electron Devices, ED-28, 1101 (1981).CrossRefGoogle Scholar
  50. [50]
    M. Orlowski, C. Mazure and F. Lau, “Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion”, IEDM Technical Digest, p. 632 (1987).Google Scholar
  51. [51]
    C. Y. Lu and J. M. Sung, “Reverse short-channel effects on threshold voltage in submicrometer salicide devices”, IEEE Electron Device Lett., EDL-10, 446 (1989).CrossRefGoogle Scholar
  52. [52]
    H. Hanafi, W. P. Noble, R. S. Bass, K. Varahramyan, Y. Lii, A. J. Dally, “A model for short channel behavior in submicron MOSFETs”, IEEE Electron Device Lett., EDL-14, 575 (1993).CrossRefGoogle Scholar
  53. [53]
    M. J. Van Dort, H. Lifka, P. C. Zalm, R. C. M. De Kruif, W. B. De Boer, P. H. Woerlee, C. A. H. Juffermans, A. J. Walker, J. W. Slotboom and N. E. B. Cowern, “A high-resolution study of two-dimensional oxidation-enhanced diffusion in silicon”, IEDM Technical Digest, p. 299 (1993).Google Scholar
  54. [54]
    B. Yu, C. Wann, E. Nowak, K. Noda, C. Hu, “Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET’s”, IEEE Trans Electron Devices, ED-44, 627 (1997).Google Scholar
  55. [55]
    H. Brut, A. Juge and G. Ghibaudo, “Physical model of threshold voltage in silicon MOS transistors including reverse short channel effect”, Electronics Letters, 31, 411 (1995).CrossRefGoogle Scholar
  56. [56]
    B. Szelag, F. Balestra and G. Ghibaudo, “Comprehensive analysis of reverse short-channel effect in silicon MOSFETs from low-temperature operation”, Electron Device letters, EDL-19, 511 (1998).CrossRefGoogle Scholar
  57. [57]
    T. Grotjohn, B. Hoefflinger, “A parametric short channel MOS transistor model for subthreshold and strong inversion current”, IEEE Trans Electron Dev., ED-31, 234, 1984.CrossRefGoogle Scholar
  58. [58]
    S. Chamberlain, S. Ramanan, “Drain induced barrier lowering analysis in VLSI MOSFET devices using two dimensional numerical simulations”, IEEE Trans Electron Dev., ED-33, 1745 (1986).CrossRefGoogle Scholar
  59. [59]
    W. Fikry, G. Ghibaudo, M. Dutoit, “Temperature dependence of drain induced barrier lowering in deep submicrometer MOSFETs”, Electron Lett., 30, 911 (1994).CrossRefGoogle Scholar
  60. [60]
    G. Bertrand, S. Deleonibus, D. Souil, C. Caillat, G. Guegan, S. Tedesco, M. Heitzmann, P. Mur, F. Balestra, “Ultimate sub 25 nm gate length NMOSFETs transport at 293K and 77K”, Silicon Nanoelectronics Workshop, Honolulu, USA (June 2000) p. 68.Google Scholar
  61. [61]
    J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, C. Hu, “Sub breakdown drain leakage current in MOSFET”, IEEE Electron Device Lett., EDL-8, 515 (1987).CrossRefGoogle Scholar
  62. [62]
    K. Kurimoto, Y. Odake, S. Odanak, “Drain leakage current characteristics due to band to band tunneling in LDD MOS devices”, IEDM Tech Digest, p. 621 (1989).Google Scholar
  63. [63]
    K. Rais, F. Balestra, G. Ghibaudo, “Temperature dependence of gate induced drain leakage in silicon MOS devices”, Electron Lett., 30, 32 (1994).CrossRefGoogle Scholar
  64. [64]
    K. Rais, G. Ghibaudo, F. Balestra, “Temperature dependence of substrate currrent in silicon CMOS devices”, Electron Lett., 29, 778 (1993).CrossRefGoogle Scholar
  65. [65]
    N. D. Arora, M. S. Sharma, “MOSFET substrate current model for circuit simulation”, IEEE Trans Electron Dev., ED-38, 1392 (1991).CrossRefGoogle Scholar
  66. [66]
    A. K. Henning, N. N. Chan, J. T. Watt, J. D. Plummer, “Substrate current at cryogenic temperatures: measurements and two-dimensional model for CMOS technology”, IEEE Trans Electron Dev., ED-34, 64 (1987).CrossRefGoogle Scholar
  67. [67]
    T. Y. Chan, P. K. Ko, C. Hu, “A simple method to characterize the substrate current in MOSFETs”, IEEE Electron device Lett., EDL-5, 505 (1984).CrossRefGoogle Scholar
  68. [68]
    B. Szelag, M. Dutoit, F. Balestra, “Hot carrier effects in deep submicron bulk silicon MOSFETs”, Solid State Electronics, 42, 42 (1997).Google Scholar
  69. [69]
    F. Balestra, Matsumoto T., Tsuno M., Koyanagi M., “New experimental findings on hot carrier effects in sub−0.1 mu m MOSFETs”, IEEE Electron Device Lett., EDL-16, 433 (1995).CrossRefGoogle Scholar
  70. [70]
    S. I. Takagi and Toriumi A., “New experimental findings on hot carrier transport under velocity saturation regime in Si MOSFETs”, Proc. IEEE/IEDM, p. 711, (1992).Google Scholar
  71. [71]
    C. Hu, S. Tarn, F-C. Hsu, P. K. Ko, T. Y. Chan, K. W. Terrill, K. Terrill “Hot-Electron Induced MOSFET Degradation-Model, Monitor, Improvement,” IEEE Trans. Electron Devices, ED-32, 375 (1985).Google Scholar
  72. [72]
    J. D. Bude and M. Matrapasqua, “Impact ionization and distribution functions in sub-micron nMOSFET technologies”, IEEE Elec. Dev. Lett., EDL-16, 439 (1995).CrossRefGoogle Scholar
  73. [73]
    J. Masunaga, Kohyama S., Konaka M., Iizuka H., “Design limitations due to substrate currents and secondary impact ionization electrons in NMOS”, Jap. J. Appl. Phys., 19, Suppl. 19-1, 93 (1979).Google Scholar
  74. [74]
    B. Marchand, B. Cretu, G. Ghibaudo, F. Balestra, D. Blachier, C. Leroux, S. Deleonibus, G. Guégan, G. Reimbold, S. Kubicek, K. DeMeyer, “Secondary impact ionization and device aging in deep submicron MOS devices with various transistor architectures”, Proc. ULIS’2000, Grenoble, p. 9 (Jan. 2000).Google Scholar
  75. [75]
    B. Marchand, D. Blachier, G. Ghibaudo, C. Leroux, F. Balestra and G. Reimbold, “Generation of hot carriers by secondary impact ionization in deep submicron devices: model and light emission characterization”, IEEE Int Reliability Physics Symposium, IRPS 2000, San Jose, CA, USA (April 2000) p. 93Google Scholar
  76. [76]
    A. Raychaudhuri, Deen J., Kwan W. S., King M., “Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFETs”, IEEE Trans. Electron Dev., ED-43, 1114 (1996).CrossRefGoogle Scholar
  77. [77]
    J. Bude, Iizuka T., Kamakura Y., “Determination of threshold energy for hot electron interface state generation”, IEDM Tech Dig., p. 865 (1996).Google Scholar
  78. [78]
    Takeda et al., Hot carrier effects in MOS devices, Academic Press, p. 123, 1995.Google Scholar
  79. [79]
    J. Wang-Ratkovic, R. Lacoe, K. MacWilliams, M. Song, S. Brown, G. Yabiku, “New understanding of LDD NMOS hot carrier degradation and device lifetime at cryogenic temperatures”, Microelectron. Reliab., 37, 1747 (1997).CrossRefGoogle Scholar
  80. [80]
    B. Cretu, F. Balestra and G. Ghibaudo, “A comparative study of hot carrier degradation in deep submicron MOSFETs at room and liquid nitrogen temperatures”, Proc. of Workshop on low temperature electronics, WOLTE 4, June 2000, ESA Editions, p. 35.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Gérard Ghibaudo
    • 1
  • Francis Balestra
    • 1
  1. 1.Laboratoire de Physique des Composants à SemiconducteursUMR CNRS, ENSERG/INPGGrenobleFrance

Personalised recommendations