Abstract
We describe a method to increase design verification coverage by guiding simulation using random input sequences. The simulation control algorithm is inspired by genetic optimization algorithms. The optimization criteria are the activation counts of various property checkers, each being concerned with a specific function of the design. Experimental results on an RTL Verilog design of some 6000 equivalent gates show that the same property coverage as in pure random simulation with uniform distributions can be achieved with half the number of simulation vectors, or, conversely, with the same number of input vectors the activation count is roughly doubled. Similar results were obtained on a 800 K gate design
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Faye, P., Cerny, E. (2001). Improved Design Verification by Random Simulation Guided by Genetic Algorithms. In: Ashenden, P.J., Mermet, J.P., Seepold, R. (eds) System-on-Chip Methodologies & Design Languages. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3281-8_8
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DOI: https://doi.org/10.1007/978-1-4757-3281-8_8
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