Abstract
Functional verification is now dominating the design cycle for many complex chips. Earlier and more thorough detection of bugs is critical for time-tomarket improvement. One technique that can help is supplementing traditional simulation with embedded checkers that monitor for correct design intent throughout both block-level and chip-level verification. This paper discusses the use of embedded checkers to assist in the functional verification of a dual-CPU PCI bridge case study design.
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© 2001 Springer Science+Business Media New York
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Switzer, S., Landoll, D., Anderson, T. (2001). Functional Verification with Embedded Checkers. In: Ashenden, P.J., Mermet, J.P., Seepold, R. (eds) System-on-Chip Methodologies & Design Languages. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3281-8_7
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DOI: https://doi.org/10.1007/978-1-4757-3281-8_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-4901-1
Online ISBN: 978-1-4757-3281-8
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