Abstract
This paper presents a mixed-language simulation environment for the languages VHDL, JAVA, and C++. The environment is implemented in JAVA and based upon a previously developed VHDL design environment consisting of a compiler, an elaborator, and a simulator. The latter was extended by open object-oriented JAVA and C++ interfaces towards mixed-language simulation capabilities. Clearly, this approach lends itself to a VHDL-centric modelling style. However, it also results in a well defined overall simulation semantics based on the proven semantic principles of VHDL. Moreover, the object-oriented JAVA and C++ interfaces enforce a much better language modelling style than traditional callback-based procedural language interfaces.
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Windisch, A., Monjau, D., Schneider, T., Mades, J., Glesner, M., Ecker, W. (2001). A VHDL-Centric Mixed-Language Simulation Environment. In: Ashenden, P.J., Mermet, J.P., Seepold, R. (eds) System-on-Chip Methodologies & Design Languages. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3281-8_4
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DOI: https://doi.org/10.1007/978-1-4757-3281-8_4
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