TCL_PLI, a Framework for Reusable, Run Time Configurable Test Benches

Abstract

As ASIC complexity keeps increasing, the time spent in design and maintenance of test benches has grown to become a disproportionately large part of the total design effort. Verilog test benches have become slow to compile and cumbersome to maintain.

This paper discusses a scripting approach to managing the test bench complexity issue. Partitioning the functionality of a test bench between Verilog and a scripting language allows for a significant reduction in compile times during ASIC verification. If done correctly, partitioning also offers great potential for re-use of test bench components.

The Tcl ianguage was chosen as a basis for implementing a library of PLI routines that allow fully customizable interpreters to be instantiated in Verilog test benches. This library allows multiple Tcl interpreters to be instantiated in a Verilog simulation. The Tcl interpreters can interact with the simulation and cause tasks to be executed in the Verilog simulation.

We have found the TCL_PLI library to be extremely valuable in speeding up our verification efforts on multi-million gate ASICs and have decided to make the library available to the general design community. The source code for the library may be obtained by contacting the authors.