A Retargetable Software Power Estimation Methodology

  • Carlo Brandolese


In the design of mixed hardware/software embedded systems, the early assessment of the power budget is a key factor to concurrently meet time-to-market and product competitiveness. An increasing contribution to the overall power consumption depends on the software portion of the design and is influenced both by the system specification style and by the target microprocessor. The proposed estimation methodology operates at an abstraction level halfway between the system language and the specific assembly language and provides power consumption figures useful for both source code analysis and modification, and for target processor selection.


Power Consumption Embed System Instruction Class Power Estimation Power Budget 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    E. Macii, M. Pedram, F. Somenzi, “High-Level Power Modeling, Estimation, and Optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, 1998.Google Scholar
  2. [2]
    T.Sato, M.Nagamatsu and H.Tago, “Power and performance simulator: ESP and its application for 100MIPS/W class RISC design,” Proceedings of IEEE Symposium on Low Power Electronic, pp. 46–47, 1994.Google Scholar
  3. [3]
    P.W.Ong and R.H.Yan, “Power-conscious software design: a framework for modeling software on hardware,” Proc. of 1994 IEEE Symposium on Low Power Electronic, pp. 36–37, San Diego, CA, Oct. 1994.Google Scholar
  4. [4]
    V. Tiwari, S. Malik and A. Wolfe, “ Power Analysis of Embedded Software: a First Step towards Software Power Minimization,” IEEE Transactions on VLSI Systems, Vol. 2, No. 4, pp. 437–445, Dec. 1994.CrossRefGoogle Scholar
  5. [5]
    V. Tiwari and M.T.-C. Lee, “Power analysis of a 32-bit Embedded Microcontroller, VLSI Design Journal, 1996.Google Scholar
  6. [6]
    J.Russell, M.F.Jacome, “Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors,” Proc. of ICCD’98, International Conference on Computer Design, Austin, Texas, USA, October, 1998.Google Scholar
  7. [7]
    C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto “Fast Software-Level Power Estimation for Design Space Exploration,” Politecnico di Milano, Tech. Report 99. 62, 1999.Google Scholar
  8. [8]
    C. Brandolese, W. Fornaciari, F. Sallee, D. Sciuto “An Energy Estimation Model for 32-bit Microprocessors,” Politecnico di Milano, Tech. Report 99. 63, 1999.Google Scholar
  9. [9]
    PEOPLE ESPRIT project n.26769, Deliverable D1.3.2.Google Scholar
  10. [10]
    PEOPLE ESPRIT project n.26769, Deliverable D1.3.3.Google Scholar
  11. [11]
    PEOPLE ESPRIT project n.26769, Deliverable D1.2.1.Google Scholar
  12. [12]
    A.Allara, M.Bombana, W. Fornaciari, F.Salice, “A Case Study in Design Space Exploration: The TOSCA Environment Applied to a Telecom Link Controller,” IEEE Design and Test of Computers, 2000, (to appear).Google Scholar

Copyright information

© Springer Science+Business Media New York 2001

Authors and Affiliations

  • Carlo Brandolese
    • 1
  1. 1.Politecnico di Milano — DEIMilanoItaly

Personalised recommendations