A VHDL Reuse Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis

Abstract

Due to the increasing complexity of digital systems, it is often desirable to start the design at higher levels of abstraction, e.g. at the algorithmic level. The necessary transformations are then performed by commercial or scientific high-level synthesis systems. In complex system design, the integration of user defined RT components (IP blocks) in the algorithmic specification is getting more and more important for the following reasons. First, several RT components appropriate for reuse may already exist. Second, the re-implementation of VHDL models emulating this behavior at the algorithmic level is expensive and time-consuming. Third, some functional and timing behavior can only be implemented at the RT level, e.g. interrupt handling, and interface components. Finally, several synthesis, simulation, and test environments which can be used for descriptions on different abstraction levels are already available. Therefore, this contribution addresses the problem of mixed abstraction level specifications for simulation and behavioral synthesis to allow the reuse of existing RT components.