A 2.5MHz Output-Rate Delta-Sigma ADC with 90dB SNR and 102dB SFDR

  • Ichiro Fujimori
  • Lorenzo Longo
  • Armond Hairapetian
  • Kazushi Seiyama
  • Steve Kosic
  • Jun Cao
  • Shu-lap Chan

Abstract

A 16-b, 2.5MHz output-rate ADC for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator employing 4-b quantizers in all stages makes quantization noise sources negligible at 8X oversampling ratio. Data weighted averaging with bi-directional rotation eliminates tones generated by multibit DAC nonlinearity to increase SFDR. Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8mm2 chip in 0.5-um CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90dB SNR in the 1.25MHz bandwidth and 102dB SFDR with 270mW power dissipation.

Keywords

Quantization Noise Total Harmonic Distortion Noise Shaping Input Switch Decimation Filter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2000

Authors and Affiliations

  • Ichiro Fujimori
    • 1
  • Lorenzo Longo
    • 2
  • Armond Hairapetian
    • 2
  • Kazushi Seiyama
    • 3
  • Steve Kosic
    • 1
  • Jun Cao
    • 2
  • Shu-lap Chan
    • 1
  1. 1.AKM SemiconductorSan DiegoUSA
  2. 2.Newport CommunicationsIrvineUSA
  3. 3.Asahi-Kasei MicrosystemsKanagawaJapan

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