A 10-bit, 20–30 MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist

  • Brian Brandt
  • Joseph Lutsky


A CMOS subranging ADC incorporates several features to enhance performance and reduce power dissipation. The combination of an extended settling period for the fine references, absolute-value signal processing, and interpolation in the comparator banks alleviates the principal speed-limiting operation. A front-end sample-and-hold amplifier (SHA) provides sustained dynamic performance at high input frequencies and performs single-ended to differential conversion with a signal gain of two and with low distortion. The SHA holds its differential output for a full clock cycle while it simultaneously samples the next single-ended input, thereby allowing it to drive two comparator banks on consecutive clock phases. The remaining analog circuits are implemented in a fully differential manner. The use of pipelining allows every input sample to be processed by the same channel, thereby avoiding the use of ping-pong techniques, while providing a conversion latency of only two clock cycles. The dynamic performance with a single-ended input approaches that of an ideal 10-bit ADC, typically providing 9.7 effective bits for low input frequencies and 9.5 bits at Nyquist. This performance level is comparable to the best reported for 10-bit CMOS ADCs with differential inputs and significantly better than those with single-ended inputs. The typical maximum DNL is ±0.4 LSB and the maximum INL is ±0.55 LSB without trimming or calibration. At 20 MSPS, the ADC power is 55mW and the SHA power is 20mW from a 5V supply. The active area is 1.6 sq. mm in a 0.5-μm double-poly, double metal CMOS technology.


Clock Cycle Input Frequency Differential Output Differential Input Fine Reference 
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Copyright information

© Springer Science+Business Media New York 2000

Authors and Affiliations

  • Brian Brandt
    • 1
  • Joseph Lutsky
    • 1
  1. 1.National Semiconductor SalemNew HampshireUSA

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