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# A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

## Abstract

This paper discusses the impact of SFDR specification on the design of A/D converter (ADC) in CMOS technology and describes the implementation of a prototype optimized for wideband SFDR performance for use in modern wireless base stations. The 6b-7b two-stage pipelined ADC using bootstrapping to linearize the sampling switch of on-chip track-hold achieves over 80 dB SFDR for signal frequencies up to 75 MHz at 50 MS/s without the need for trimming, calibration and dithering. INL is 1.3LSB, DNL is 0.8LSB. The 6b and 7b sub-ADC’s are made efficient with averaging and folding. In 0.61.1m CMOS, the 16mm^{2}ADC dissipates 850mW from 3.3V supply.

## Keywords

Gain Error Spurious Free Dynamic Range Dynamic Element Match Thermometer Code Coarse Channel## Preview

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