Abstract
Voltage controlled oscillators and prescalers are critical high speed building blocks in RFsynthesizers and PLL’s. For wireless applications, major VCO-design criteria are low voltage, low power, low phasenoise, wide and/or linear tunability and small area. Primary key to LC-VCO optimization is optimal LC-tank design. 0.35jum CMOS VCO designs, fulfilling GSM and DECT phasenoise requirments, are presented. Solutions to generate quadrature outputs are discussed. Main prescaler design goal is low power and low voltage design. Multi modulus prescalers using dynamic CMOS flipflops can be used for minimal power consumption. Finally some mixed-mode aspects of RFCMOS circuit design for single-chip RF synthesizers and PLL’s are discussed.
The erratum of this chapter is available at http://dx.doi.org/10.1007/978-1-4757-3198-9_19
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© 2000 Springer Science+Business Media New York
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Tiebout, M. (2000). Design and Optimization of RFCMOS-Circuits for Integrated PLL’s and Synthesizers. In: van de Plassche, R.J., Huijsing, J.H., Sansen, W. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3198-9_15
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DOI: https://doi.org/10.1007/978-1-4757-3198-9_15
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5002-4
Online ISBN: 978-1-4757-3198-9
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