Abstract
In this section WLDDs are applied to verification circuits described by Hardware Description Languages (HDLs) [70]. A set of datapath operations is defined that allows one to effectively verify high-level HDLs, like VHDL. The verification technique directly translates HDL constructs to WLDDs. For this development, first two operations are introduced, modulo operation and division. It has been proven that none of the “usual” WLDD-types can represent the general division function efficiently (see Section 7.3). Nevertheless, the algorithms for these closely related operators work very well in practice. All experiments in this section have been carried out on a SUN Ultra-170 workstation with 256 MByte of main memory.
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© 2000 Springer Science+Business Media Dordrecht
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Drechsler, R. (2000). Verification of HDLs. In: Formal Verification of Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3184-2_8
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DOI: https://doi.org/10.1007/978-1-4757-3184-2_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-4985-1
Online ISBN: 978-1-4757-3184-2
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