High-Level Power Estimation Methodology Applied for Processor-Level DTSE

  • Paul Lippens
  • Natalino Busa
  • Jos Huisken
  • Rafael Peset Llopis


The huge integration capability of modern technologies allows very complex systems on a single IC. The design of such ICs is a very complex task due to the challenge of managing their complexity. There are two approaches to deal with complexity. Firstly, to increase the level of abstraction by using architectural synthesis tools. Secondly, to partition these ICs into several different types of sub-designs, such as embedded microprocessors and DSPs. Figure 4. 1 gives an overview of a typical digital design flow. A behavioural VHDL description is made of the design, based on the specifications. This description is partitioned into several sub-designs, which are translated by several different architectural synthesis tools, and/or manually by a designer into a Register-Transfer level (RTL) VHDL description. The logic synthesis tool transforms the latter into a VHDL gate netlist, which is the input to layout synthesis.


Power Dissipation Power Estimation Design Flow Very Long Instruction Word Signal Flow Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    A. Aho, R. Sethi, and J. Ullman, “Compilers: Principles, Techniques and Tools”, Addison-Wesley, 1988.Google Scholar
  2. [2]
    R. Bajwa, M. Hiraki, H. Kojima, D. Gorny, K. Nitta, A. Shridhar, K. Seki, K. Sasaki, “Instruction buffering to reduce power in processors for signal processing”, IEEE Trans, on VLSI Systems, Vol. 5, No. 4, pp. 417–424, Dec. 1997.CrossRefGoogle Scholar
  3. [3]
    N. Bellas, I. Hajj, C. Polychronopoulos, G. Stamoulis, “Architectural and compiler support for energy reduction in the memory hierarchy of high-performance microprocessors”, Proc. IEEE Intnl. Symp. on Low Power Design, Monterey CA, pp. 70–75, Aug. 1998.Google Scholar
  4. [4]
    A. Bogliolo et al. , “Adaptive Least Mean Square Behavioral Power Modeling”, Proc. ED&TC, 1997, pp. 404–10.Google Scholar
  5. [5]
    R. Burch et al. , “A Monte Carlo Approach for Power Estimation”, IEEE Trans, on VLSI, Mar. 1993, pp. 63–71.Google Scholar
  6. [6]
    F. Catthoor, “Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions”, invited paper, Proc. 1st ACM/IEEE Design and Test in Europe Conf. , Paris, France, pp. 709–714, Feb. 1998.Google Scholar
  7. [7]
    F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, “Global communication and memory optimizing transformations for low power signal processing systems”, IEEE workshop on VLSI signal processing, Oct. 1994.Google Scholar
  8. [8]
    F. Catthoor and M. Cupak. “Efficient functional validation of system-level loop transformations for multi-media applications”, Proc. Electronic Circuits and Systems Conference, Bratislava, Slovakia, Sep. 1997, pp 39–43.Google Scholar
  9. [9]
    N. Deo. “Graph Theory with applications to engineering and Computer Science”, Prentice-Hall, 1914.Google Scholar
  10. [10]
    European Broadcast Union, “Radio Broadcast Systems; Digital Audio Broadcasting to Mobile Portable and Fixed Receivers”, prETS 200401, Vol. Final Draft 1994.Google Scholar
  11. [11]
    Le Floch, B. , Halbert-Lassalle, R. , and Castelain, D. , “Digital sound broadcasting to mobile receivers”, IEEE Transactions on Consumer Electronics 35, 3, Aug. 1989.Google Scholar
  12. [12]
    J. Kin, M. Gupta, W. Mangione-Smith, “The filter cache: an energy efficient memory structure”, Proc. 30th Int. Symp. on Microarchitecture, pp. 184–193, Dec. 1997.Google Scholar
  13. [13]
    D. Kuck, “The Structure of Computers and Computation”, Wiley, 1978.Google Scholar
  14. [14]
    RE. Landman and J. M. Rabaey, “Architectural Power Analysis: The Dual Bit Type Method”, IEEE Trans, on VLSI, Jun. 1995, pp. 173–87.Google Scholar
  15. [15]
    D. Liu and C. Svensson, “Power Consumption in CMOS VLSI Chips”, IEEE J. of Solid State Circ. , Jun. 1994, pp. 663–70.Google Scholar
  16. [16]
    J. L. v. Meerbergen et al. , “PHIDEO: High-Level Synthesis for High Througput Applications”, J. of VLSI Signal Processing, Vol. 9, 1995, pp. 89–104.CrossRefGoogle Scholar
  17. [17]
    G. De Micheli, “Synthesis and optimization of digital circuits”, McGraw Hill, 1994.Google Scholar
  18. [18]
    F. N. Najm, “Transition Density: A New Measure of Activity in Digital Circuits”, IEEE Trans, on CAD, Feb. 1993, pp. 310–23.Google Scholar
  19. [19]
    M. Nemani and F. N. Najm, “Towards a High-Level Power Estimation Capability”, IEEE Trans, on CAD, Jun. 1996, pp. 588–98.Google Scholar
  20. [20]
    Peset Llopis, R. , “A New Approach in High-Level Power Estimation”, Proc. DATE, 1998.Google Scholar
  21. [21]
    Power Compiler of Synopsys, 1996Google Scholar
  22. [22]
    H. J. M. Veendrick, “Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits”, IEEE J. of Solid-State Circ, Aug. 1984, pp. 468–73Google Scholar
  23. [23]
    “IEEE Standard VHDL Language Reference Manual”.IEEE Std 1076, 1993.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2000

Authors and Affiliations

  • Paul Lippens
    • 1
  • Natalino Busa
    • 1
  • Jos Huisken
    • 1
  • Rafael Peset Llopis
    • 1
  1. 1.Philips Research Laboratories EindhovenThe Netherlands

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