Abstract
The huge integration capability of modern technologies allows very complex systems on a single IC. The design of such ICs is a very complex task due to the challenge of managing their complexity. There are two approaches to deal with complexity. Firstly, to increase the level of abstraction by using architectural synthesis tools. Secondly, to partition these ICs into several different types of sub-designs, such as embedded microprocessors and DSPs. Figure 4. 1 gives an overview of a typical digital design flow. A behavioural VHDL description is made of the design, based on the specifications. This description is partitioned into several sub-designs, which are translated by several different architectural synthesis tools, and/or manually by a designer into a Register-Transfer level (RTL) VHDL description. The logic synthesis tool transforms the latter into a VHDL gate netlist, which is the input to layout synthesis.
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Lippens, P., Busa, N., Huisken, J., Llopis, R.P. (2000). High-Level Power Estimation Methodology Applied for Processor-Level DTSE. In: Catthoor, F. (eds) Unified low-power design flow for data-dominated multi-media and telecom applications. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3182-8_4
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DOI: https://doi.org/10.1007/978-1-4757-3182-8_4
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