Instruction Scheduling for Clustered VLIW Processors

  • Rainer Leupers
Chapter

Abstract

This chapter presents a code optimization technique for a special class of processor data paths, which we call clustered VLIW. Here, a cluster denotes a piece of the data path with functional units (FUs) and a local register file. Such a data path architecture is frequently found in multimedia processors and ASIPs. We will focus on the problem of instruction scheduling. Fig. 4.1 shows how this phase relates to the overall compilation flow.

Keywords

Critical Path Control Step List Schedule Schedule Length Instruction Schedule 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media Dordrecht 2000

Authors and Affiliations

  • Rainer Leupers
    • 1
  1. 1.University of DortmundGermany

Personalised recommendations