A 3.3 V 15-bit Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL-Applications

  • Yves Geerts
  • Michiel Steyaert
  • Willy Sansen


The design of a high-resolution high-speed delta-sigma analog-to-digital converter is presented. An overview of the performance of different topologies is shown. For the selected 2–1–1 cascade topology, a system level optimisation is performed. Several circuit non-idealities are analysed to arrive at building block specifications. The design of the building blocks is treated. Measurement results of the 3.3 V 15-bit ΔΣ with a signal bandwidth of 1.1 MHz are discussed.


Switch Resistance Reference Voltage Harmonic Distortion Signal Bandwidth Capacitive Load 
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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Yves Geerts
    • 1
  • Michiel Steyaert
    • 1
  • Willy Sansen
    • 1
  1. 1.ESAT-MICASKU LeuvenHeverleeBelgium

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