Interrupts and Branch Mispredictions

  • Amos R. Omondi


This chapter deals with the handling of interrupts in pipelined machines and with recovery in the event of branch mispredictions. The first section is a discussion of basic implementation techniques, the second consists of a number of case studies, and the third is a summary.


Register File Program Counter Destination Register Execution Unit Page Fault 
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Copyright information

© Springer Science+Business Media New York 1999

Authors and Affiliations

  • Amos R. Omondi
    • 1
  1. 1.Department of Computer ScienceFlinders UniversityAdelaideAustralia

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