Data Flow: Detecting and Resolving Data Hazards

  • Amos R. Omondi


A pipeline can fail to achieve its maximum speedup if there are discontinuities in the supply of instructions or data. Discontinuities in the flow of instructions have been covered in the preceding chapter; in this chapter, we shall discuss the problem of discontinuities in the flow of data as well as corresponding solutions. The data-flow discontinuities arise mainly from two sources: one is a mismatch between the rate at which the pipeline requests data and the rate at which the data is delivered to the pipeline; the other is data hazards (or data dependences) that occur between instructions in the pipeline when one instruction cannot proceed because its progress depends on that of another instruction. The basic problem of mismatching rates is largely solved by the use of appropriate high-speed intermediate storage (cache, registers, etc.) and other techniques discussed in Chapter 3 and will not be considered further. This chapter is therefore devoted to just the hazards and related issues.


Functional Unit Mapping Table Physical Register Register File Cache Line 
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  1. 1.
    Acosta, RD., J. Kjelstrup, and H.C. Torng. 1986. An instruction issuing approach to enhancing performance in multiple functional unit processors. IEEE Transactions on Computers, C-35(9):815–828.CrossRefGoogle Scholar
  2. 2.
    Alpert, D. and D. Avnon. 1993. Architecture of the Pentium microprocessor. IEEE Micro, 13(3):11–21.CrossRefGoogle Scholar
  3. 3.
    AMD 1987. Am29000 Streamlined Instruction Processor: User’s Manual. Advanced Micro Devices, Sunnyvale, California, USA.Google Scholar
  4. 4.
    AMD. 1997. AMD-K6 MMX Processor. Advanced Micro Devices, Sunnyvale, California.Google Scholar
  5. 5.
    Alsup, M. 1990. Motorola’s 88000 family architecture. IEEE Micro, 10(3):48–66.CrossRefGoogle Scholar
  6. 6.
    Asprey, T. et al. 1993. Performance features of the PA7100 microprocessor. IEEE Micro, 13(3):22–35.CrossRefGoogle Scholar
  7. 7.
    Becker, M.C. et al. 1993. The PowerPC 601 microprocessor. IEEE Micro, 13(5):54–68.CrossRefGoogle Scholar
  8. 8.
    Chen, T.C. 1964. The overlap design of the IBM System/360 Model 92 central processing unit. In: Proceedings, AFIPS Fall Joint Computer Conference, vol. 26, part II, pp 73–80.Google Scholar
  9. 9.
    Christie, D. 1996. Developing the AMD-K5 architecture. IEEE Micro, 16(2):16–26.CrossRefGoogle Scholar
  10. 10.
    Circello, J. et al. 1995. The superscalar architecture of the MC68060. IEEE Micro, 15(2):10–21.CrossRefGoogle Scholar
  11. 11.
    Diefendorfi, K. and M. Allen, 1992. Organization of the Motorola 88110 superscalar RISC microprocessor. IEEE Micro, 12(4):40–63.CrossRefGoogle Scholar
  12. 12.
    Diep, T.A., C. Nelson, and J.P. Shen. 1995. Performance evaluation of the PowerPC 620 microarchitecture. In: Proceedings, 22nd Annual International Symposium on Computer Architecture, pp 163–174.CrossRefGoogle Scholar
  13. 13.
    Edmondson, J.H. et al. 1995. Internal organization of the Alpha 21164, a 300MHz 64-bit quad-issue CMOS RISC microprocessor. Digital Technical Journal, 7(1):119–135.Google Scholar
  14. 14.
    Edmondson, J.H., P. Rubinfield, R. Preston, and V. Rajagopalan. 1995. Superscalar instruction execution in the Alpha 21164 microprocessor. IEEE Micro, 15(2):33–43.CrossRefGoogle Scholar
  15. 15.
    Grohoski, G.F. 1990. Machine organization of the IBM RISC System/6000 processor. IBM Journal of Research and Development, 36(1):37–58.CrossRefGoogle Scholar
  16. 16.
    Keller, R.M. 1975. Look-ahead processor. ACM Computing Surveys, 7(4):66–72.CrossRefGoogle Scholar
  17. 17.
    McMahon, S.C., M. Bluhm, and R.A. Garbay. 1995. 6x86: the Cyrix solution to executing x86 binaries on a high performance machine. Proceedings of the IEEE, 83(12): 1664–1672.CrossRefGoogle Scholar
  18. 18.
    Melear, C. 1989. The design of the 8800 RISC family. IEEE Micro, 9(2):26–38.CrossRefGoogle Scholar
  19. 19.
    MIPS. 1996. MIPS R10000 Microprocessor User’s Manual. MIPS Technologies, Mt. View, California.Google Scholar
  20. 20.
    Morris, D. and R.N. Ibbett. 1979. The MU5 Computer System. Springer-Verlag, New York.Google Scholar
  21. 21.
    Omondi, A. R. 1994. Ideas for the design of multithreaded pipelines. In: R.H. Halstead, G.R. Gao, R.A. Iannucci, and B. Smith, Editors, Multithreaded Computer Architecture: A Summary of the State of the Art. Kluwer Academic Publishers, Boston.Google Scholar
  22. 22.
    Popescu, V. et al. 1991. The Metaflow architecture. IEEE Micro, June: 10–13, 63–73.Google Scholar
  23. 23.
    Potter, M., M. Vaden, J. Young, and N. Ullah. 1994. Resolution of control and data dependencies in the PowerPC 601. IEEE Micro, 14(5):18–29.CrossRefGoogle Scholar
  24. 24.
    Sites, R.L. 1993. Alpha AXP Architecture. Communications of the ACM, 36(2):33–44.CrossRefGoogle Scholar
  25. 25.
    Smith, J.E. 1989. Dynamic instruction scheduling and the Astronautics ZS-1. IEEE Computer, July:21–35Google Scholar
  26. 26.
    Smith, J.E., and G.S. Sohi. 1995. The microarchitecture of superscalar processors. Proceedings of the IEEE, 83(12): 1609–1624.CrossRefGoogle Scholar
  27. 27.
    Song, S.P., M. Denman, and J. Chang. 1994. The PowerPC 604 microprocessor. IEEE Micro, 14(5) :8–17.CrossRefGoogle Scholar
  28. 28.
    Thornton, J.E. 1970. Design of a Computer: The Control Data 6600. Scott, Foresman, and Co., Illinois, USA.Google Scholar
  29. 29.
    Tomasulo, R.M. 1967. An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of Research and Development, 11(1):25–33.zbMATHCrossRefGoogle Scholar
  30. 30.
    Tremblay, M. , D. Greenley, and K. Normoyle. 1995. The design of the microarchitecture of the UltraSPARC-1. Proceedings of the IEEE, 83(12): 1653–1663.CrossRefGoogle Scholar
  31. 31.
    Trioani, M. et al. 1985. The VAX 8600 I Box: A pipelined implementation of the VAX architecture. Digital Technical Journal, 1:24–42.Google Scholar
  32. 32.
    Weiss, S. and J.E. Smith. 1984. Instruction issue logic in pipelined supercomputers. IEEE Transactions on Computers, vol. C-33, no. 9 (Sep. 1984), ppGoogle Scholar
  33. 33.
    Williams, T., N. Patkar, and G. Shen. 1995. SPARC64: A 64-b 64-activeinstruction out-of-order-execution MCM processor. IEEE Journal of Solid-State Circuits, 30(11):1215–1226.CrossRefGoogle Scholar
  34. 34.
    Yeager, K.C. 1996. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28–40.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 1999

Authors and Affiliations

  • Amos R. Omondi
    • 1
  1. 1.Department of Computer ScienceFlinders UniversityAdelaideAustralia

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