Abstract
To this point, we have concentrated mostly on behavioral modeling of a digital system. Behavioral models are more concerned with describing the abstract functionality of a module, regardless of its actual implementation. Logic level modeling is used to model the logical structure of a module, specifying its ports, submodules, logical function, and interconnections in a way that directly corresponds to its implementation. This chapter presents the Verilog constructs that allow us to describe the logical function and structure of a system.
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Ā© 1998 Springer Science+Business Media New York
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Thomas, D.E., Moorby, P.R. (1998). Logic Level Modeling. In: The VerilogĀ® Hardware Description Language. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2896-5_4
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DOI: https://doi.org/10.1007/978-1-4757-2896-5_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2898-9
Online ISBN: 978-1-4757-2896-5
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