Skip to main content

System-Level Verification Issues

  • Chapter
  • 102 Accesses

Abstract

This chapter discusses system-level verification, focusing on the issues and opportunities that arise when macros are integrated into a complete system on a chip. The topics are:

  • The importance of verification

  • Test plan

  • Application-based verification

  • Fast prototype testing

  • Gate-level verification

  • Verification tools

  • Specialized hardware for system verification

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   74.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 1998 Springer Science+Business Media New York

About this chapter

Cite this chapter

Keating, M., Bricaud, P. (1998). System-Level Verification Issues. In: Reuse Methodology Manual for System-on-a-Chip Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2887-3_11

Download citation

  • DOI: https://doi.org/10.1007/978-1-4757-2887-3_11

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4757-2889-7

  • Online ISBN: 978-1-4757-2887-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics