Abstract
This chapter discusses system-level verification, focusing on the issues and opportunities that arise when macros are integrated into a complete system on a chip. The topics are:
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The importance of verification
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Test plan
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Application-based verification
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Fast prototype testing
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Gate-level verification
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Verification tools
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Specialized hardware for system verification
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© 1998 Springer Science+Business Media New York
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Keating, M., Bricaud, P. (1998). System-Level Verification Issues. In: Reuse Methodology Manual for System-on-a-Chip Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2887-3_11
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DOI: https://doi.org/10.1007/978-1-4757-2887-3_11
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2889-7
Online ISBN: 978-1-4757-2887-3
eBook Packages: Springer Book Archive