High-Frequency CMOS Prescalers

  • J. Craninckx
  • M. Steyaert
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 439)


As already stated in the introduction, two high-frequency building blocks of a PLL frequency synthesizer require extra effort to be implemented in a standard CMOS process. The voltage-controlled oscillator has already been discussed in chapters 3 to 5. This chapter deals with the other circuit that also operates at the full output frequency, i.e. the frequency divider. The several types of frequency dividers have already been listed is section 2.4.4. A divider that can handle all integer division numbers must be a programmable counter. But because of the large amount of logic required to make a function like that, its speed is limited, and operation at more than 1 GHz in a standard CMOS process is certainly impossible. Therefore a prescaler can be positioned before the normal frequency divider to reduce the required speed. This prescaler circuit divides by a fixed number, usually a power of 2, and can operate at higher frequencies since the critical path can be kept short. The required speed of the subsequent stages is lowered by the prescaler division number, but also the smallest frequency step has increased by that number. For a constant frequency resolution, the reference frequency must be lowered, which of course has its disadvantages. A dualmodulus prescaler can divide by two different numbers, and is used together with a pulse- and a swallow-counter (see figure 2.25) to resolve this problem. Also in the design of fractional-N division systems, dual-modulus prescalers are used.


Frequency Divider Input Frequency Frequency Synthesizer NAND Gate Transistor Size 
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Copyright information

© Springer Science+Business Media Dordrecht 1998

Authors and Affiliations

  • J. Craninckx
    • 1
  • M. Steyaert
    • 2
  1. 1.Alcatel MietecBelgium
  2. 2.Katholieke Universiteit LeuvenBelgium

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