In this chapter, our DTSE approach will be demonstrated on several realistic applications, both in the domain of video and image processing, as well as in the ATM domain. We will show the effect on the system power budget, memory size and system simulation time. The absolute power and area figures used below are estimated for a particular library and technology. As such they should only be used as indications. What is most important are the relative differences in the data for the different design alternatives. For instance, in a custom optimized architecture for a complete H.263 video conferencing decoder, one of our in-depth design studies has shown that data-path and controller related power is negligable compared to the contribution of the frame memory accesses. Moreover, we have been able to reduce the maximal power consumption related to these frame memory accesses by a factor 9 for the worst-case mode (PB) of the video decoder. This has been achieved solely by applying our system-level DTSE exploration methodology and it is complementary to other power savings feasible at lower abstraction levels by voltage and technology scaling. These substantial effects are confirmed in the other demonstrators.
KeywordsPower Consumption Cache Size Power Budget Cache Strategy Frame Buffer
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