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CMOS VLSI Engineering pp 307–344Cite as

SOI-Technology ST-SPICE

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Abstract

As described in the previous chapters, SOI CMOS technology has been regarded as another major VLSI technology in addition to bulk CMOS technology. VLSI circuits using SOI CMOS technology have been reported increasingly. Since the performance of SOI CMOS devices is quite different from that of the bulk ones, SOI VLSI circuits have demonstrated unique phenomena as described in Chapter 3. When designing SOI VLSI circuits, the SPICE CAD program designed for bulk CMOS devices may not be sufficient for circuit simulation. In this chapter, by including the analytical device models of deep-submicron fully-depleted SOI CMOS devices described in the last two chapters, SOI-Technology— ST-SPICE1 suitable for CAD of SOI CMOS VLSI circuits is described. Starting from the basic concepts of the SPICE program, analytical device models of deep-submicron fully-depleted SOI CMOS devices used in ST-SPICE for CAD of VLSI circuits are explained. In the final portion of this section, usage of the ST-SPICE CAD program for analyzing the steady state and transient behaviors of SOI CMOS circuits is presented.

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Authors and Affiliations

  1. National Taiwan University, Taiwan

    James B. Kuo & Ker-Wei Su

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  1. James B. Kuo
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  2. Ker-Wei Su
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© 1998 Springer Science+Business Media Dordrecht

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Kuo, J.B., Su, KW. (1998). SOI-Technology ST-SPICE. In: CMOS VLSI Engineering. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2823-1_6

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  • DOI: https://doi.org/10.1007/978-1-4757-2823-1_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5057-4

  • Online ISBN: 978-1-4757-2823-1

  • eBook Packages: Springer Book Archive

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