Abstract
In this chapter, SOI CMOS technology is described. Starting from the evolution of SOI technology, various SOI substrate and isolation techniques are introduced. Then, a 0.25μm SOI CMOS fabrication processing sequence is described, followed by major SOI CMOS device structures. In the final portion of this chapter, special-purpose SOI technologies including DRAM, BiCMOS, and power are described.
Keywords
Chemical Mechanical Polishing Polysilicon Layer Breakdown Electric Field Silicon Nitride Layer Bury Oxide Layer
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Preview
Unable to display preview. Download preview PDF.
References
- [1]J. E. A. Maurits, “SOS Wafers— Some Comparisons to Silicon Wafers,” IEEE Trans. Elec. Dev., Vol. 25, No. 8, pp. 859–863, Aug. 1978.CrossRefGoogle Scholar
- [2]H. W. Lam, “Silicon on Insulating Substrates— Recent Advances,” IEDM Dig., pp. 348–351, 1983.Google Scholar
- [3]S. L. Partridge, “The Current Status of Silicon-On-Insulator Technologies— A Comparison,” IEDM Dig., pp. 428–430, 1986.Google Scholar
- [4]J.-P. Colinge, “Thin-Film SOI Technology: The Solution to Many Submicron CMOS Problems,” IEDM Dig., pp. 817–820, 1989.Google Scholar
- [5]A. J. Auberton-Herve, “SOI Technologies Applications: Trends in VLSI,” SOI Con]. Dig., pp. 149–150, 1990.Google Scholar
- [6]H. Vogt, G. Burbach, J. Belz, and G. Zimmer, “Silicon-on-Insulator Development in Europe,” Sol. St. Tech., pp. 79–83, Feb. 1991.Google Scholar
- [7]J.-P. Colinge, “Problems and Issues in SOI CMOS Technology,” SOI Conf. Dig., pp. 126–127, 1991.Google Scholar
- [8]D. Feijoo, A. P. Mills, A. R. Kortan, J. B. Sapjeta, C. M. Hsieh and G. E. Carver, “Comparative Materials Characterization of SOI Wafers Produced by Competing Technologies,” SOI Conf. Dig., pp. 38–39, 1993.Google Scholar
- [9]S. Kawamura, “Ultra-Thin-Film SOI Technology and its Application to Next Generation CMOS Devices,” SOI Conf. Dig., pp. 6–7, 1993.Google Scholar
- [10]A. J. Auberton-Herve, “SOI: Materials to Systems,” IEDM Dig., pp. 3–10, 1996.Google Scholar
- [11]H. H. Hosack, T. W. Houston, and G. P. Pollack, “SIMOX Silicon-on-Insulator: Materials and Devices,” Sol. St. Tech., pp. 61–66, Dec. 1990.Google Scholar
- [12]G. Ryding, T. H. Smick, M. Farley, B. F. Cordts, R. P. Dolan, L. P. Allen, B. Mathews, W. Wray, B. Amundsen, and M. J. Anc, “The Ibis 1000 SIMOX Production Implanter,” SOI Conf. Dig., pp. 436–439, 1997.Google Scholar
- [13]K. Izumi, M. Doken, and H. Ariyoshi, “C.M.O.S. Devices Fabricated on Buried SiO 2 Layers Formed by Oxygen Implantation into Silicon,” Elec. Let., Vol. 14, No. 18, pp. 593–594, Aug. 1978.CrossRefGoogle Scholar
- [14]S. Nakashima and K. Izumi, “Analysis of Buried Oxide Layer Formation and Mechanism of Threading Dislocation Generation in the Substoichiometric Oxygen Dose Region,” J. Mater. Res., Vol. 8, No. 3, pp. 523–534, March 1993.CrossRefGoogle Scholar
- [15]T. Nakai, H. Shinyashiki, T. Shingyouji, Y. Yamaguchi, T. Nishimura, and Y. Akasaka, “Reduction of Dislocations in a SIMOX Film by Controlling the Annealing Sequence,” SOI Conf. Dig., pp. 120–121, 1991.Google Scholar
- [16]J. Jablonski, M. Saito, M. Imai, and S. Nakashima, “Gettering Layer Formation in Low-Dose SIMOX Wafers,” SOI Conf. Dig., pp. 34–35, 1995.Google Scholar
- [17]S. Nakashima, T. Katayama, Y. Miyamura, A. Matsuzaki, M. Imai, K. Izumi, and N. Ohwada, “Thickness Increment of Buried Oxide in a SIMOX Wafer by High-Temperature Oxidation,” SOI Conf. Dig., pp. 71–72, 1994.Google Scholar
- [18]Y. Kunii, S. Nanashima, M. Nagase, and K. Izumi, “Reduction in Surface Roughness of SIMOX Substrate by H 2 Annealing,” SOI Conf. Dig., pp.42–43, 1996.Google Scholar
- [19]C. W. Mueller, and P. H. Robinson, “Grown-Film Silicon Transistors on Sapphire,” IEEE Proc, pp.1487–1490, Dec. 1964.Google Scholar
- [20]D. C. Mayer, P. K. Vasudev, A. E. Schmitz and R. E. Kastris, “A High-Speed Submicrometer CMOS/SOS Process in Spear Material,” IEDM Dig., pp.676–679, 1985.Google Scholar
- [21]P. M. Zavracky, D.-P. Vu, and M. Batty, “Silicon-on-Insulator Wafers by Zone Melting Re-crystallization,” Sol. St. Tech., pp.55–57, Apr. 1991.Google Scholar
- [22]T. J. Stultz and J. F. Gibbons, “Arc Lamp Zone Melting and Recrystallization of Si Films on Oxidized Silicon Substrates,” Appl. Phys. Let, Vol. 41, No. 9, pp. 824–826, Nov. 1982.CrossRefGoogle Scholar
- [23]Y. Kobayashi, A. Fukami and T. Suzuki, “Zone-Melting Recrystallization of Polycrystalline Silicon Films on Fused Silica Substrates Using RF-Heated Carbon Susceptor,” IEEE Elec. Dev. Let, Vol. 4, No. 5, pp. 132–134, May 1983.CrossRefGoogle Scholar
- [24]A. J. Auberton-Herve, J. P. Joly, P. Jeuch, J. Gautier, and J. M. Hode, “Device Performances of a Submicron SOI Technology,” IEDM Dig., pp. 808–811, 1984.Google Scholar
- [25]M. Yoshimi, K. Suguro, M. Takahashi, T. Hamasaki, T. Inoue, T. Yoshii, K. Taniguchi and H. Tango, “Stacked SOI CMOS Fabricated with Seeding Lateral Epitaxy,” Symp. VLSI Tech. Dig., pp. 26–27, 1985.Google Scholar
- [26]J. B. Lasky, S. R. Stiffler, F. R. White, and J. R. Abernathey, “Silicon-on-Insulator (SOI) by Bonding and Etch-Back,” IEDM Dig., pp. 684–687, 1985.Google Scholar
- [27]K. R. Sarma, and S. T. Liu, “Silicon-on-Quartz for Low Power Electronic Applications,” SOI Conf. Dig., pp. 117–118, 1994.Google Scholar
- [28]E. E. King, D. H. Huang, P. Leonov, L. J. Palkuti, G. J. Campisi, H. L. Hughes, and D. J. Godbey, “CMOS on Bonded Wafers Fabricated using a Novel Si-Ge Etch Stop,” SOI Conf. Dig., pp. 112–113, 1991.Google Scholar
- [29]N. Sato, K. Sakaguchi, K. Yamagata, T. Atoji, Y. Fujiyama, J. Nakayama and T. Yonehara, “High-Quality Epitaxial Layer Transfer (ELTRAN) by Bond and Etch-Back of Porous Si,” SOI Conf. Dig., pp. 176–177, 1995.Google Scholar
- [30]B. H. Lee, C. J. Kang, J. H. Lee, S. I. Yu, K. W. Lee, K. C. Park and T. E. Shim, “A Novel CMP Method for Cost-Effective Bonded SOI Wafer Fabrication,” SOI Conf. Dig., pp. 60–61, 1995.Google Scholar
- [31]H. J. Hovel, “Silicon-on-Insulator Substrates: Status and Prognosis,” SOI Conf. Dig., pp. 1–3, 1996.Google Scholar
- [32]M. Bruel, “Silicon on Insulator Material Technology,” Elec. Let, Vol. 31, No. 14, pp. 1201–1202, July 1995.CrossRefGoogle Scholar
- [33]M. Haond, and O. Le Neel, “Lateral Isolation in SOI CMOS Technology,” Sol. St Tech., pp. 47–52, July 1991.Google Scholar
- [34]M. Haond and O. Le Neel, “Rounded Edge Mesa for Submicron SOI CMOS Process,” SOI Conf. Dig., pp. 132–133, 1990.Google Scholar
- [35]P. V. Gilbert and S.-W. Sun, “A PELOX Isolated Sub-0.5Micron Thin-Film SOI Technology,” Sym. VLSI Tech. Dig., pp.37–38, 1995.Google Scholar
- [36]T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, “Experimental 0.25/xm Gate Fully Depleted CMOS/SIMOX Process Using a New Two-Step LOCOS Isolation Technique,” IEEE Trans. Elec. Dev., Vol. 42, No. 8, pp.1481–1486, Aug. 1995.CrossRefGoogle Scholar
- [37]C.-L. Huang, and G.J. Grula, “Degradation Characteristics of STI and MESA-Isolated Thin-Film SOI CMOS,” IEEE Elec. Dev. Let, Vol. 18, No. 10, pp. 474–476, Oct. 1997.CrossRefGoogle Scholar
- [38]L. K. Wang, J. Seliskar, T. Bucelot, A. Edenfeld, and N. Haddad, “Enhanced Performance of Accumulation Mode 0.5μm CMOS/SOI Operated at 300K and 85K,” IEDM Dig., pp. 679–682, 1991.Google Scholar
- [39]Y. Kado, T. Ohno, M. Harada, K. Deguchi and T. Tsuchiya, “Enhanced Performance of Multi-GHz PLL LSIs Using Sub-l/4-micron Gate Ultrathin Film CMOS/SIMOX Technology with Synchrotron X-ray Lithography,” IEDM Dig., pp. 243–246, 1993.Google Scholar
- [40]G. G. Shahidi, C. Blair, K. Beyer, T. Bucelot, T. Buti, P. N. Chang, S. Chu, P. Coane, J. Comfort, B. Davari, R. Dennard, S. Furkay, H. Hovel, J. Johnson, D. Klaus, K. Kiewtniack, R. Logan, T. Lii, P. A. McFarland, N. Mazzeo, D. Moy, S. Neely, T. Ning, M. Rodriguez, D. Sadana, S. Stiffler, J. Sun, F. Swell, and J. Warnock, “A Room Temperature 0.1μm CMOS on SOI,” Symp. VLSI Tech. Dig., pp. 27–28, 1993.CrossRefGoogle Scholar
- [41]T. Iwamatsu, Y. Yamaguchi, Y. Inoue, T. Nishimura, and N. Tsubouchi, “CAD-Compatible High-Speed CMOS/SIMOX Gate Array Using Field-Shield Isolation,” IEEE Trans. Elec. Dev., Vol. 42, No. 11, pp. 1934–1939, Nov. 1995.CrossRefGoogle Scholar
- [42]J.-P. Colinge, M.-H. Gao, A. Romano, H. Maes and C. Claeys, “Silicon-on-Insulator Gate-All-Around MOS Device,” SOI Conf. Dig., pp. 137–138, 1990.Google Scholar
- [43]T. Tanaka, H. Horie, S. Ando and S. Hijiya, “Analysis of P+ Poly Si Double-Gate Thin-Film SOI MOSFETs,” IEDM Dig., pp. 683–686, 1991.Google Scholar
- [44]D. Hisamoto, T. Kaga, Y. Kawamoto and E. Takeda, “A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET,” IEEE Elec. Dev. Let, Vol. 11, No. 1, pp. 36–38, Jan. 1990.CrossRefGoogle Scholar
- [45]C. T. Nguyen, S. C. Kuehne, P. Renteln, and S. S. Wong, “Quasi-SOI MOSFETs Using Selective Epitaxy and Polishing,” IEDM Dig., pp. 341–344, 1992.Google Scholar
- [46]I.-K. Kim, W. -T. Kang, J.-H. Lee, S. Yu, S.-C. Lee, K. Yeom, Y.-G. Kim, D.-H. Lee, G. Cha, B. H. Lee, S.-I. Lee, K.-C. Park, T.-E. Shim and C.-G. Hwang, “Advanced Integration Technology for a Highly Scalable SOI DRAM with SOC (Silicon-On-Capacitors),” IEDM Dig., pp. 605–608, 1996.Google Scholar
- [47]S. Nakamura, H. Horie, K. Asano, Y. Nara, T. Fukano, and N. Sasaki, “Giga-bit DRAM Cells with Low Capacitance and Low Resistance Bit-Lines on Buried MOSFET’s and Capacitors by Using Bonded SOI Technology- Reversed-Stacked-Capacitor (RSTC) Cell-,” IEDM Dig., pp. 889–892, 1995.Google Scholar
- [48]K. Terada, T. Ishijima, T. Kubota, and M. Sakao, “A New DRAM Cell with a Transistor on a Lateral Epitaxial Silicon Layer (TOLE Cell),” IEEE Trans. Elec. Dev., Vol. 37, No. 9, pp. 2052–2057, Sept. 1990.CrossRefGoogle Scholar
- [49]W.-L. M. Huang, K. M. Klein, M. Grimaldi, M. Racanelli, S. Ramaswami, J. Tsao, J. Foerstner, and B.-Y. C. Hwang, “TFSOI Complementary BiCMOS Technology for Low Power Applications,” IEEE Trans. Elec. Dev., Vol. 42, No. 3, pp. 506–512, March 1995.CrossRefGoogle Scholar
- [50]R. S. Ronen, M. R. Splinter, and R. E. Tremain, “High-Voltage SOS/MOS Devices and Circuit Elements: Design, Fabrication, and Performance,” IEEE J. Sol. St. Ckts, Vol. 11, No. 4, pp. 431–442, Aug. 1976.CrossRefGoogle Scholar
- [51]S. Matsumoto, T. Yachi, H. Horie, and Y. Arimoto, “A Novel High-Speed Quasi-SOI Power MOSFET with Suppressed Parasitic Bipolar Effect Fabricated by Reversed Silicon Wafer Direct Bonding,” IEDM Dig., pp. 949–951, 1996.Google Scholar
Copyright information
© Springer Science+Business Media Dordrecht 1998