In this chapter several issues concerning system-level synthesis starting from VHDL specifications are discussed. We concentrate here on aspects which are characteristic to the synthesis of hardware components. Specifications containing subprograms and interacting processes are of main interest in this context. The last section is devoted to the problem of specifying timing constraints and of hardware synthesis under restrictions imposed by such constraints.
KeywordsAdvance Feature Data Path Tabu Search Algorithm Simulation Cycle Synthesis Tool
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