This section defines the modeling of two separate classes of models, each with different variations. These include:
  1. 1.

    Memory Model. The traditional memory model, where all the information is stored in a variable, is demonstrated. In addition, the modeling of very large memories (GBytes) is illustrated using a cache like approach and a dynamic/paging method.

  2. 2.

    Wire Model. This is a model of a zero ohm resistor (bridge or pass-through component) that exemplifies the concept of a break before make. It is a good learning example as it demonstrates the concepts of drivers, delta times, and the generate statement. Many users have requested this model because it reflects real hardware interconnections.

  3. 3.

    Error Injector Model. The wire model was modified to create an error injector, where a third port is used to identify the type of stuck-at (or none) fault to apply at the pass through switch.



Resistor Model Fault Injection Page Cache Wire Model Disk Paging 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 1997

Authors and Affiliations

  • Ben Cohen

There are no affiliations available

Personalised recommendations