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A 12 bit, 50 MSample/s Cascaded Folding & Interpolating ADC

  • Pieter Vorenkamp
  • Raf Roovers

Abstract

This paper presents the analysis, design and experimental results of a 12 bits, 50 MSample/s Analog-to-Digital Converter, based on a Cascaded Folding and Interpolating architecture. The ADC is optimized for digital telecommunication applications. The integrated Track & Hold circuit enables SNR > 66 dB and THD < 72 dB, measured over an input signal bandwidth of 70 MHz. The ADC is realized in a 13 GHz, 1 μm BiCMOS process and measures 7 mm2, while dissipating 300 mW from a single 5.0 V supply.

Keywords

Solid State Circuit Spurious Free Dynamic Range Folding Signal Folding Factor Classical Folding 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Pieter Vorenkamp
    • 1
  • Raf Roovers
    • 1
    • 2
  1. 1.Philips SemiconductorsCaenFrance
  2. 2.Philips Research LaboratoriesEindhovenThe Netherlands

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