Abstract
This paper presents the analysis, design and experimental results of a 12 bits, 50 MSample/s Analog-to-Digital Converter, based on a Cascaded Folding and Interpolating architecture. The ADC is optimized for digital telecommunication applications. The integrated Track & Hold circuit enables SNR > 66 dB and THD < 72 dB, measured over an input signal bandwidth of 70 MHz. The ADC is realized in a 13 GHz, 1 μm BiCMOS process and measures 7 mm2, while dissipating 300 mW from a single 5.0 V supply.
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References
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© 1997 Springer Science+Business Media Dordrecht
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Vorenkamp, P., Roovers, R. (1997). A 12 bit, 50 MSample/s Cascaded Folding & Interpolating ADC. In: van de Plassche, R.J., Huijsing, H.H., Sansen, W. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2602-2_5
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DOI: https://doi.org/10.1007/978-1-4757-2602-2_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5185-4
Online ISBN: 978-1-4757-2602-2
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