A 12 bit, 50 MSample/s Cascaded Folding & Interpolating ADC
This paper presents the analysis, design and experimental results of a 12 bits, 50 MSample/s Analog-to-Digital Converter, based on a Cascaded Folding and Interpolating architecture. The ADC is optimized for digital telecommunication applications. The integrated Track & Hold circuit enables SNR > 66 dB and THD < 72 dB, measured over an input signal bandwidth of 70 MHz. The ADC is realized in a 13 GHz, 1 μm BiCMOS process and measures 7 mm2, while dissipating 300 mW from a single 5.0 V supply.
KeywordsSolid State Circuit Spurious Free Dynamic Range Folding Signal Folding Factor Classical Folding
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