Abstract
Emerging telecom systems such as ADSL, VDSL demand state—of—the—art high speed and high resolution A/D and D/A converters. Moreover, cost and power consumption issues require the use of specific A/D and D/A architectures to achieve the wanted resolution at the required speed for the minimum power. In the first part of this paper an overview is given of various A/D and D/A converter architectures used in Alcatel telecom systems over the past 15 years. Emphasis is placed on the evolution of A/D and D/A converters for today’s ADSL applications. Then design considerations for high speed and high resolution pipelined A/D converters for future VDSL technology will be addressed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Z.Y. Chang et al, “A CMOS analog Front End circuit for an FDM—based ADSL system” proceedings IEEE ISSCC’96
J. Sevenhans et al, “A Versatile digital signal processor in 1.2μ cmos with on chip d/a and a/d conversion serving 4 speech channels in a new generation subscriber line circuit” proceedings ESSCIRC’90
D. Sallaerts et al, “A 160 kbit/s Transceiver for Digital subscriber loop” proceedings IEEE lSSCC’86
Thomas Hack , “IQ Sampling Yields Flexible Demodulators” RF Design, April 1991 pp40–50
Hans.J. Dressler, “Interpolative bandpass A/D conversion” Elsevier, Signal Processing 22 1991
J. Vanneuville et al, “A transistor only sigma—delta a/d convertor for a cmos speech codec” proceedings ESSCIRC’90
Y.L. Cheung et al, “A Sampled—Data Switched—Current Analog 16—Tap FIR Filter with Digitalally Programmable Coefficients in 0.8µm CMOS” proceedings IEEE ISSCC’96 SA19.2 pp314–315
T.B. Cho and P.Gray, “A 10—b 20Msamples/s 35mW pipeline A/D converter,” IEEE J. Sol id—State Circuits, Vol.30, NO.3, pp 166–172, March 1995
D.W. Cline and P. Gray, “A Power optimized 13—b 5Msamples/s analog to digital converter in 1.2um CMOS,” IEEE J. Solid—State Circuits, Vol.31, NO.3, pp294–303, March 1996
W-H Song et al, “A 10—b 20—Msamples/s low power CMOS ADC,” IEEE J. Solid—State Circuits, Vol.30, NO.5, pp514–521, May 1995
K. Nakamura et al, “A 85mW, 10b, 40Msamples/s CMOS parallel—pipelined ADC,” IEEE.J. Solid—State Circuits, Vol.30, NO.3, pp173–183, March 1995
M. K. Mayes and S.W.Chin, “Monolithic low—power 16b 1 Msamples/s self—calibrating pipeline ADC,” proceedings IEEE ISSCC’96 SA 19.1 pp312–313
P.C. Yu and H.S.Lee, “A 2.5 V 12b 5Ms/s pipelined CMOS ADC,” proceedings IEEE ISSCC’96 SA19.2 pp314–315
S.I. Lim et al, “A 12b 10Mhz 250mW CMOS AD converter,” proceedings IEEE ISSCC’96 SA 19. 2 pp316–317
K. Y. Kim et al, “A 10b 100Ms/s CMOS AD converter,” proceedings IEEE CICC’96 SA20. 3 pp419–422
[18]. K. Nagaraj et al, “A 8—bit 50 Ms/s pipelined A/D converter with an area and power efficient architecture,” proceedings IEEE CICC’96 SA20.3 pp423–426
J. Yang and H.S. Lee, “A CMOS 12—b 4Mhz pipelined A/D converter with commutative feedback capacitor,” proceedings IEEE CICC’96 SA20.3 pp427–430
Y.M Lin, B. Kim and P. Graly, “A 13—b 2.5 Mhz self—calibrated pipelined A/D converters in 3um CMOS,” IEEE J. Solid—State Circuits, Vol.26, NO.4, pp628–635, April 1991
[ADI] Analog Devices, “12—bit, 41 Msps Monolithic A/D converter
[BBI] Burr Brown, “12—bit, 40Mha sampling Analog—to—Digital converter”
L. Singer and T. Brooks, “A 14—bit 10Mhz calibration—free CMOS pipelines ADC,” IEEE V LSI’ 96 pp94–95, 1996
B. Nauta and A. G. W. Venes, “A 70—Ms/s 110—mW 8—b CMOS folding and interpolating A/D converter,” IEEE J. Solid—State Circuits, Vol 30, NO.12, pp 1302–1307, Dec. 1995
A. Venes and R. Van de Plassche, “An 80Mhz 80mW 8b folding A/D converter with distributed T/H preprocessing,” IEEE ISSCC’96 pp318–319, 1996
R. Jewett et al, “A 12b 128Msamples/s ADC with 0.05LSB DNL” proceedings IEEE ISSCC’97 pp138–139
S-U Kwak et al, “A 15b 5Msamples/s low—spurious CMOS ADC” proceedings IEEE ISSCC’96 pp146–147
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1997 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Sevenhans, J., Chang, ZY. (1997). Architectures and Circuits for A/D and D/A Conversion in CMOS Integrated Systems for Telecom Applications. In: van de Plassche, R.J., Huijsing, H.H., Sansen, W. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2602-2_4
Download citation
DOI: https://doi.org/10.1007/978-1-4757-2602-2_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5185-4
Online ISBN: 978-1-4757-2602-2
eBook Packages: Springer Book Archive